Patent
1995-06-07
1998-10-20
Lall, Parshotam S.
395800, G06F 938
Patent
active
058260552
ABSTRACT:
An system and method for retiring instructions in a superscalar microprocessor which executes a program comprising a set of instructions having a predetermined program order, the retirement system for simultaneously retiring groups of instructions executed in or out of order by the microprocessor. The retirement system comprises a done block for monitoring the status of the instructions to determine which instruction or group of instructions have been executed, a retirement control block for determining whether each executed instruction is retirable, a temporary buffer for storing results of instructions executed out of program order, and a register array for storing retirable-instruction results. In addition, the retirement control block further controls the retiring of a group of instructions determined to be retirable, by simultaneously transferring their results from the temporary buffer to the register array, and retires instructions executed in order by storing their results directly in the register array. The method comprises the steps of monitoring the status of the instructions to determine which group of instructions have been executed, determining whether each executed instruction is retirable, storing results of instructions executed out of program order in a temporary buffer, storing retirable-instruction results in a register array and retiring a group of retirable instructions by simultaneously transferring their results from the temporary buffer to the register array, and retiring instructions executed in order by storing their results directly in the register array.
REFERENCES:
patent: 4903196 (1990-02-01), Pomerene et al.
patent: 4942525 (1990-07-01), Shntani et al.
patent: 5067069 (1991-11-01), Fite et al.
patent: 5072364 (1991-12-01), Jardine et al.
patent: 5109495 (1992-04-01), Fite et al.
patent: 5167026 (1992-11-01), Muray et al.
patent: 5214763 (1993-05-01), Blaner et al.
patent: 5222240 (1993-06-01), Patel
patent: 5226126 (1993-07-01), McFarland et al.
patent: 5251306 (1993-10-01), Tran
patent: 5317720 (1994-05-01), Stamm et al.
patent: 5345569 (1994-09-01), Tran
patent: 5355457 (1994-10-01), Shebanow et al.
patent: 5390355 (1995-02-01), Horst
patent: 5398330 (1995-03-01), Johnson
patent: 5442757 (1995-08-01), McFarland et al.
patent: 5487156 (1996-01-01), Popescu et al.
patent: 5560032 (1996-09-01), Nguyen et al.
HPS, A New Microarchitecture: Rationale and Introduction, Yale N. Patt, Wen-Mei Hwu and Michael C. Shebanow, The 18th Annual Workshop on Microprogramming, Pacific Grove, California, Dec. 3-6, 1985, IEEE Computer Society Order No. 653, pp. 103-108.
Critical Issues Regarding A High Performance Mircoarchitecture, Yale N. Patt, Wen-Mei Hwu and Michael C. Shebanow, The 18th Annual Workshop on Microprogramming, Pacific Grove, California, Dec. 3-6, 1985, IEEE Computer Order No. 653, pp. 109-116.
Hwu, Wen-mei and Yale Patt, "HPSm, a High Performance Restricted Data Flow Architecture Having Minimal Functionality", Proceedings of the 18th International Symposium on Computer Architecture, pp. 297-306, Jun. 1986.
Gee, Jeff, Stephen W. Melvin and Yale Patt, "The Implemenatation of Prolig via VAX 8600 Microcode", Proceedings of Micro 19, New York City, pp. 1-7, Oct. 1986.
Yale N. Patt, Stephen W. Melvin, Wen-mei Hwu, Michael C. Shebanow, Chein Chen, Jia-juin Wei, "Run-Time Generation of HPS Microinstructions From a VAX Instruction Stream", Proceedings of Micro 19 Workshop, New York, New York, pp. 1-7, Oct. 1986.
Hwu, Wen-mei, Steve Melvin, Mike Shenbanow, Chein Chen, Jea-Juin Wei, Yale Patt "An HPS Implementatin of VAX: Initial Design and Analysis", Proceedings of the Nineteenth Annual Hawaii International Conference on System Sciences, pp. 282-291, 1986.
Hwu et al., "Experiments with HPS, a Restricted Data Flow Microarchtecture for High Performance Computers", Compcon 86, 1986.
Wilson, James E., Steve Melvin, Michael Shenbanow, Wen-mei Hwu and Yale N. Patt, "On Turning the Microarchitecture of an HPS Implementation of the VAX", Proceedings of Micro 20, pp. 162-167, Dec. 1987.
Hwu, Wen-mei and Yale Patt, "Design Choices for the HPSm Microprocessor Chip", Proceedings of the Twentieth Annual Hawaii International Conference on System Sciences, pp. 330-336, 1987.
Hwu, Wen-mei and Yale N. Patt, "HPSm2: A Refined Single-Chip Microengine", HICSS '88, pp. 30-40, 1988.
Butler, Michael and Yale Patt, "An Improved Area-Efficient Register Alias Table for Implementing HPS", University of Michigan, Ann Arbor, Michigan, Jan. 1990.
Uvieghara, G.A., W.Hwu, Y. Makagome, D.K. Jeong, D. Lee, D.A. Hodges, T. Patt, "An Experimental Single-Chip Data Flow CPU", Symposium on ULSI Circuits Design Digest of Technical Papers, May 1990.
John L. Hennessy and David A. Patterson, Computer Architecture a Quantitative Approach, Ch. 6.4, 6.7 and p. 449, 1990.
Lightner et al., "The Metaflow Architecture", IEEE Micro Magazine, pp. 11-12, 63-68, Jun. 1991.
Dywer, A Multiple, Out-of-Order Instruction Issuing System for Superscalar Processors, (All), Aug. 1991.
Bruce D. Lightner and Gene Hill, "The Metaflow Lightning Chipset*", pp. 13-16, IEEE Publication, 1991.
Uvieghara, Gregory A., Wen-mei Hwu, Yoshinobu Nakagome, Deog-Kyoon Jeong, David D. Lee, David D. Hodges and Yale Patt, "An Experimental Single-Chip Data Flow CPU", IEEE Journal of Solid-State Circuits, vol. 27, No. 1, pp. 17-28, Jan. 1992.
IEEE Micro, "The Metaflow Architecture", Val Popescu et al, vol. 11, No. 3, Jun. 1991, pp. 10-13 and 63-73.
Proceedings of the 18th Annual International Symposium on Computer Architecture, "Single Instruction Sttream Parallelism Is Greater than Two", M. Butler et al, May 1991, pp. 276-286.
Popescu et al., "The Metaflow Architecture", Jun. 1991, pp. 10-73.
Pelet et al, "Future Trends in Microprocessors Out-of-Order Execution, Spec. Branching and Their CISC Performance Potential", Mar. 1991.
Deosaran Trevor
Garg Sanjiv
Wang Johannes
Lall Parshotam S.
Seiko Epson Corporation
Vu Viet
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