Loop latency compensated PLL filter

Details Loop latency compensated PLL filter Loop latency compensated PLL filter

1999-05-13

2001-05-22

Tokar, Michael (Department: 2819)

Coded data generation or conversion

Phase or time of phase change

C341S143000

Reexamination Certificate

active

06236343

ABSTRACT:

FIELD OF INVENTION
Invention relates to phase-locked loop circuits (PLLs), and more particularly to PLLs in storage devices, such as disk drives.
BACKGROUND OF INVENTION
In the presence of initial disturbances such as phase and frequency steps, the optimal phase-locked loops (PLL) filter is known to have time varying form. Typical PLL filter designs based on frequency response techniques cannot handle time varying filters and hence generate sub-optimal results. It has been recognized for some time now that state space methods in general and Kalman filtering techniques in particular can be used to design and analyze synchronizers or PLL, such as surveyed in “Phase-Locked Loops,” S. C. Gupta, Proceedings of the IEEE, vol. 63, no. 2, February 1975. More specifically, Kalman filtering theory enables us to derive optimal synchronizer structures for a given phase disturbance model, generate the time varying and steady state filter gain parameters, and calculate the time varying performance of the synchronizer. Usually, the filter gain parameters as well as the performance measure are found recursively using the Kalman recursions as described, for example, in “DPLL Bit Synchronizer With Rapid Acquisition Using Adaptive Kalman Filtering Techniques,” P. F. Driessen, IEEE Transactions on Communications, vol. 42, no. 9, September 1994 and in “Modeling of A PRML Timing Loop As a Kalman Filter,” G. S. Christiansen, GlobeCom '94, vol. 2, Nov. 28-Dec. 2, 1994.
An undesirable property of many discrete-time synchronizers is the inherent presence of loop delay, such as described in “Effect of Loop Delay on Stability of Discrete-Time PLL”, J. W. M. Bergmans, IEEE Transactions on Communications, vol. 42, no. 4, April 1995, which not only makes the synchronizer less stable but also degrades the performance of the synchronizer. Moreover, conventional PLLs in magnetic recordings use lower signal-to-noise ratio (SNR) values and compensate for this loss by providing more coding and error correction coding (ECC). The typical PLL loop latency in present PRML read channels is about 15-25 cells.
FIG. 1
, for example, illustrates a general system block diagram of a typical prior art PLL
10
(known as second order type II) used in most disk drives that use sampled detection. Typical PLL
10
comprises an analog-to-digital converter (A/D)
12
receiving an input analog signal
11
. AID
12
is coupled to a phase detector
14
to detect an estimated phase error
15
in PLL
10
. Estimated phase error
15
is provided as input to a proportional integral (PI) filter
29
comprising a first multiplier
16
, a first accumulator
18
, a second multiplier
30
and a first adder
22
. Latency compensated phase error output
23
of PI filter
29
is then coupled to a second accumulator
24
, also known as voltage controlled oscillator (VCO), that sums a phase component (alpha) from multiplier
30
and a delayed frequency component (beta) from a first accumulator
18
of PI filter
32
. Second accumulator
24
provides as output a filtered phase error control signal
27
to drive a phase mixer
28
.
As the signal to noise ratio (SNR) becomes lower, the phase error or jitter increases thereby degrading the PLL performance
10
. Conventional designs of PLL such as PLL
10
focus on minimizing the latency in the PLL loop, and not on compensating the effect of latency. There is therefore an urgent need to optimize the PLL performance with respect to disturbance sources, and with respect to the loop latency.
SUMMARY OF INVENTION
A loop latency compensated PLL filter provided in accordance with the principles of this invention includes two additional feedback terms comprising a delayed phase compensation term and state compensation term. A linear, discrete time optimal synchronizers for pulse amplitude modulation (PAM) systems is provided using Kalman filtering techniques assuming Gauss-Markov phase disturbance model.
In loop latency compensated PLL filter, two additional feedback terms, a state compensation and a delayed phase compensation signal, are provided as input of a proportional integral filter (PI filter) of loop latency compensated PLL. Accordingly, the PI filter input comprises two additional compensation input signals: the delayed phase signal and the state signal, in addition to a phase estimated error output from a phase detector, that are coupled to the input of the PI filter. Consequently, PI filter thus is able to provide a latency compensated phase error control output that is fedback to control a phase mixer to generate a square waveform used to drive an A/D of the PLL in accordance with the principles of this invention. The loop latency compensated PLL of this invention thus minimizes the jitter of the PLL circuit, provides higher format efficiency, and also has reduced sensitivity to large bursty noises.


REFERENCES:
patent: 5654711 (1997-08-01), Fujimori
patent: 5825253 (1998-10-01), Mathe et al.
patent: 5838270 (1998-11-01), Kiriaki
patent: 5949361 (1999-09-01), Fischer et al.
patent: 6028544 (2000-02-01), Zarubinsky et al.
J.W.M. Bergmans, “Effect of Loop Delay on Stability of Discrete-Time PLL”, 4/95 IEEE Transactions on Circuits and Systems-I:Fundamental Theory and Applications, vol. 42, No. 4.
Peter F. Driessen, “DPLL Bit Synchronizer with Rapid Acquisition Using Adaptive Kalman Filtering Techniques”, Sep. 1994, IEEE Transactions on Communications, vol. 42, No. 9.
Grabt S. Christiansen, “Modeling of PRML Timing Loop as a Kalman Filter”, GLOBECOM '94, vol 2, Nov. 28—Dec. 2, 1994.

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