Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Charge transfer device
Reexamination Certificate
1999-03-22
2001-12-04
Tran, Minh Loan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Charge transfer device
C257S240000, C257S223000
Reexamination Certificate
active
06326655
ABSTRACT:
RELATED APPLICATION DATA
The present application claims priority to Japanese Application No. P10 074392 filed Mar. 23, 1998 which application is incorporated herein by reference to the extent permitted by law.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a solid state imaging device and particularly, to an MOS-type solid state imaging device having an MOS transistor (MOS referred to by this specification is a general term for a conductive layer/an insulating film/semiconductor structure) and its manufacturing method.
2. Description of the Related Art
FIG. 1
shows a block diagram of an essential portion of a MOS-type solid state imaging device with a so-called FD (Floating Diffusion)-type arrangement. The arrangement of the solid state imaging device is such that a plurality of unit pixels
101
(only one unit pixel is shown in
FIG. 1
) are disposed in a plurality of rows and columns, that is, in the horizontal and vertical directions, and each unit pixel
101
has a sensor unit consisting of a photoelectric conversion element by a photo-diode
102
and in which a signal electric charge obtained by the sensor unit is read out by an FD read-out MOS transistor
103
and the signal electric charge is amplified to a signal voltage or signal electric current by an FD amplifying MOS transistor
104
in each unit pixel.
In the arrangement of
FIG. 1
, it is a case of an arrangement in which the signal amplification is carried out in each unit pixel
101
, but as the block diagram of an essential portion in
FIG. 2
shows, a so-called column amplifier-type solid state imaging device in which an amplifier is disposed at, for example, every common column can be made.
In the column amplifier-type solid state imaging device too, there is provided an arrangement such that a plurality of unit pixels
201
(also in
FIG. 2
, one unit pixel is only shown) are respectively disposed in a plurality of rows and columns, that is, in the horizontal and vertical directions, and each unit pixel
201
has a photo-diode
202
as the photoelectric conversion element in its sensor unit, and in which an MOS transistor
203
for reading out a signal electric charge accumulated in the photo-diode
202
and a selecting MOS transistor
204
for reading out the signal electric charge to a vertical signal line
208
are formed and a column amplifier
205
is disposed at every vertical signal line
208
.
The photoelectric conversion element, that is, the photo-diode and the MOS transistor which carries out read-out of the electric charge therefrom at the sensor unit in each of the unit pixels
101
and
201
of these MOS-type solid state imaging devices are made a complex arrangement in which one semiconductor region constituting the photo-diode, for example, a cathode region is made to serve as a source region of the MOS transistor.
FIG. 6
shows a schematic plan pattern view of a sensor unit S and a forming portion of the MOS transistor which reads out the signal electric charge therefrom.
The sensor unit S is formed with a photoelectric conversion region
1
formed to constitute the photo-diode. The MOS transistor (MOS) is comprised of the photoelectric conversion region
1
as its source, a semiconductor region
2
as its drain, which is formed with a predetermined distance, that is, a distance corresponding to a channel length away from the photoelectric conversion region and a gate electrode
3
formed between them through a gate insulating film (not shown).
The sensor unit S is formed in one corner of, for example, the unit pixels
101
and
202
respectively explained in connection with FIG.
1
and FIG.
2
and the gate electrode
3
is formed to be displaced toward other circuit device forming portion side in the unit pixel.
The above-mentioned MOS-type imaging device has, because of being comprised of the MOS transistor, an advantage of fundamentally reducing power consumption in comparison with, for example, a CCD (charge-coupled device)-type imaging device, but there have occurred some problems in the fact that a signal electric charge is completely read out from the above-mentioned sensor unit at a low read-out voltage by the read-out transistor.
SUMMARY OF THE INVENTION
An object of the present invention is to solve these problems. That is, the inventor of the present invention has investigated that the cause of incompleteness of the read-out voltage and in reading out the signal electric charge in the read-out MOS transistor resides in the positional relations between the sensor unit and the gate portion of the read-out MOS transistor. Specifically, it has been investigated that according to the conventional structure, because the disposed position of the gate electrode is formed apart from a potential dip for a signal electric charge in the photoelectric conversion region of the sensor unit, when the signal electric charge is read out, it becomes necessary to increase the read-out voltage, that is, the gate voltage for the read-out MOS transistor or it is difficult to completely read out the signal electric charge and so, in order to completely carry out the read-out, a further large read-out voltage is needed.
The present invention is, based on the investigation, to provide a solid state imaging device to be able to nearly completely read out the signal electric charge from the sensor unit with a low read-out voltage and particularly, an MOS imaging device.
An arrangement of a solid state imaging device according to the present invention is such that a plurality of unit pixels, each having a sensor unit with a photoelectric conversion region in which a first semiconductor region of a second conductivity-type is formed in a semiconductor region of a first conductivity-type, and on a surface thereof, a high impurity concentration layer of a first conductivity type is formed and an insulating gate transistor for reading out a signal electric charge from the sensor portion, are disposed.
Then, the photoelectric conversion region in the sensor unit is so arranged as to form a single potential dip for the signal electric charge and the gate electrode for the insulating gate transistor is formed into such a pattern that the middle portion thereof in a channel width direction is positioned above the central portion of the potential dip or its vicinity.
As mentioned above, in the present invention, because the potential dip to be formed in the photoelectric conversion region is singly formed as well as the gate electrode of the MOS transistor for reading out the signal electric charge is formed to extend above the central portion of the potential dip, that is, on the top of the dip or at a position nearly as the top, it is possible to read out the signal electric charge from a portion lower than the most highest portion of a potential barrier in the periphery of the dip, thereby making it possible to lower the read-out voltage and further, completely carry out the read-out of the signal electric charge.
REFERENCES:
patent: 4148048 (1979-04-01), Takemoto et al.
patent: 5199053 (1993-03-01), Hirama
patent: 5286989 (1994-02-01), Yonemoto
patent: 5357129 (1994-10-01), Kamimura
patent: 5539226 (1996-07-01), Kawamoto et al.
Sonnenschein Nath & Rosenthal
Sony Corporation
Tran Minh Loan
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