Process of forming self-aligned interconnects for semiconductor

Details Process of forming self-aligned interconnects for semiconductor Process of forming self-aligned interconnects for semiconductor

1989-05-01

1991-10-08

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 46, 437186, 437187, 437228, H01L 21302

Patent

active

050554271

ABSTRACT:
A novel process is provided to fabricate interconnections (46c) in transistors (14) having self-aligned, planarized contacts (46s, 40g, 46d) in a novel, completely self-aligned configuration. The process of the invention permits higher packing densities, and allows feature distances to approach 0.5 .mu.n and lower.
A unique combination of masks in conjunction with a multi-layer structure (28) formed on the surface of a semiconductor wafer (16), the multi-layer structure including a buried etch-stop layer therein (28b), defines the source (18), gate (22), and drain (20) elements and their geometry relative to each other and to interconnects. Polysilicon plug (40, 46) contacts through slots in the multi-structure layer permit vertical contact to be made to the various elements. Silicidation (56) of the polysilicon plugs reduces series resistance in the vertical direction and permits strapping of N.sup.+ and P.sup.+ polysilicon plugs.

REFERENCES:
patent: 4424621 (1984-01-01), Abbas et al.
patent: 4534826 (1985-08-01), Goth et al.
patent: 4589952 (1986-05-01), Behringer et al.
patent: 4631806 (1986-12-01), Poppert et al.
patent: 4721689 (1988-01-01), Chaloux Jr. et al.
patent: 4746630 (1988-05-01), Hui et al.
patent: 4789648 (1988-12-01), Chow et al.

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