Method for forming a multilevel interconnect structure on a semi

Details Method for forming a multilevel interconnect structure on a semi Method for forming a multilevel interconnect structure on a semi

1990-09-10

1991-10-08

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437187, 437192, 437194, H01L 2190

Patent

active

050554263

ABSTRACT:
A method for forming lower levels of metal in multilevel interconnects involves initial formation of a poly-metal dielectric layer having grooves and contact holes, subsequent deposition of a covering layer of metal, masking of the covering layer and etching to produce protruding pillars, and addition of an intermetal dielectric layer surrounding the pillars. The process steps produce a metal level having integral studs or posts, conduction strips and contacts.

REFERENCES:
patent: 4451326 (1984-05-01), Gwozdz
patent: 4764484 (1988-08-01), Mo
patent: 4789648 (1988-12-01), Chow et al.
patent: 4840923 (1989-06-01), Flagelto et al.

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