MOS Semiconductor process utilizing a two-layer oxide forming te

Details MOS Semiconductor process utilizing a two-layer oxide forming te MOS Semiconductor process utilizing a two-layer oxide forming te

1978-05-19

1979-02-20

Rutledge, L. Dewayne

Metal treatment

Compositions

Heat treating

29571, 148174, 148187, 357 23, 357 54, 427 93, 427 95, H01L 21324, H01L 21265, H01L 2131

Patent

active

041405480

ABSTRACT:
Process for the manufacture of MOS devices by providing wafer of P-semiconductor grade silicon in a deposition reactor. The wafer is heated to a temperature of approximately 950.degree. C. while subjecting the wafer to dry oxygen gas to produce between a very thin layer (50-250A) of silica (SiO.sub.2) on a surface of the wafer. While elevating the temperature of the wafer to approximately 1000.degree. C., the chamber is purged with nitrogen and then hydrogen gas. After an introduction of carbon dioxide gas into the chamber, silane (SiH.sub.4) or dichlorosilane gas is bled into the chamber. The silane reacts with the CO.sub.2 to deposit SiO.sub.2 on the previously formed thermal SiO.sub.2. The two layers of SiO.sub.2 may then be annealed to provide a highly coherent, defect-free gate oxide for MOS integrated circuits.

REFERENCES:
patent: 3158505 (1964-11-01), Sandor
patent: 3184329 (1965-05-01), Burns
patent: 3243314 (1966-03-01), Lehman et al.
patent: 3532539 (1970-10-01), Tokuyama et al.
patent: 3547786 (1970-12-01), Rigo
patent: 3580745 (1971-05-01), Kooi et al.
patent: 3615873 (1971-10-01), Sluss et al.
patent: 3627589 (1971-12-01), Sprague
patent: 3925107 (1975-12-01), Goula et al.
Goula, R. A., "Composite Dielectric Layer" I.B.M. Tech. Discl. Bull., vol. 14, No. 9, Feb. 1972, p. 2609.
Bratter et al., "High-Temperature Pyrolytic Deposition Process".
Ibid., vol. 15, No. 2, Jul. 1972, p. 685.
Burkhardt et al., "Post-Oxidation Annealing . . . Levels" Ibid., vol. 18, No. 3, Aug. 1975, p. 753.

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