Process for fabricating semiconductor integrated circuit devices

Details Process for fabricating semiconductor integrated circuit devices Process for fabricating semiconductor integrated circuit devices

1989-05-09

1991-10-08

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 57, 437 58, H01L 21265

Patent

active

050554204

ABSTRACT:
After contact holes for the P- and N-type source or drain regions of P- and N-channel MOSFETs have been made at a common step, an N-type impurity is ion-implanted into at least the N-type source or drain regions through the contact holes. The N-type impurity is annealed to fornm an N-type region which is deeper than the N-type source or drain regions. During the annealing treatment, the N-type source or drain regions are covered with an insulating film.

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Toker, J. R., "Fabrication and Characterization of E-Beam Defined MOSFETs . . . " IEDM Tech Dig. Dec. 1980, pp. 768-771.

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