Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2000-06-19
2001-05-22
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S185170, C365S189040
Reexamination Certificate
active
06236591
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
At the present time, diverse applications are being used in which values, represented by a counter reading, for example, are recorded in a nonvolatile form. The values are preferably stored in read-only memories, such as EPROMs, EEPROMs and flash EPROMs, i.e. in memories which can be erased and can have information written to them again. The memories and the circuits determining the value, and also circuits that control the value determination and storage procedure, are usually produced in integrated circuits. The integrated circuits or the semiconductor chip that contains them are currently usually embedded in card-like data media for the purpose of better handling. In most cases, the value represents a monetary credit value that can only be reduced for example, in the case of telephone cards, but may also be increased again in the case of cash cards. Alternatively, the value may be the reading on an odometer in a vehicle, for example.
Published, Non-Prosecuted German Patent Application DE 36 38 505 A1 describes a value counter which is in the form of a volatile binary counter whose counter reading can be stored in nonvolatile form in an EEPROM after the data medium has been used. At the start of the data medium being used, the content of the EEPROM is transferred to the binary counter again as an initial counter reading. The counter can be operated only in the direction in which the value represented by the counter reading is reduced. Since the value of the data medium can thus not be increased, there is only a small incentive for manipulation by fraudulent parties.
A data medium described in International Patent Disclosure WO 96/10810 is intended to be rechargeable, and it should thus also be possible to increase its value. In this instance, the counter is formed using EEPROM memory cells, and is organized such that it operates as a multistage counter using the abacus principle. In order to rule out manipulation by changing the counter reading, two counters of identical construction are provided which are used alternately whenever the counter reading is increased. Although the counter configuration is very reliable, it requires a relatively large number of memory cells and thus has a high area requirement.
Published, European Patent Disclosure EP 0 398 545 A1 discloses an odometer which is likewise formed using a binary counter whose counter reading is stored in nonvolatile form in memory cells at regular intervals. Since it is not possible to erase and rewrite information to nonvolatile memory cells, particularly EEPROM cells, as often as desired, a number of identical memory areas are provided which are used successively, whenever the “life” of the previous memory area has come to an end. To distinguish the memory area that is current in each case, control memory cells are provided whose state is evaluated.
In the known counter, when there is a change of memory area, the new memory area is first erased. The current counter reading is then entered in the memory area. The associated control memory cell is subsequently programmed. Finally, the control memory cell for the old memory area is erased. A change of memory area requires a total of four erasing and programming operations to be carried out, which takes up a considerable amount of time. This presents a problem in an odometer in which a change of memory is necessary only after 20,000 km, for example.
This is not acceptable for telephone cards, however, in which each unit consumed necessitates a change of counter reading, and hence a change of memory area.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for reliably changing a value stored in a nonvolatile memory, and a circuit configuration for this purpose, that overcome the above-mentioned disadvantages of the prior art methods and devices of this general type, which reliably changes a value stored in a memory, and an integrated circuit configuration for this purpose which, in the first instance, needs only a small number of nonvolatile memory cells, and, in the second instance, allows a rapid change of memory area.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for reliably changing a value of a data medium, which contains the steps of:
providing a memory having at least two nonvolatile memory areas for storing a currently valid value, each of the memory areas having at least one associated nonvolatile control memory cell whose state defines an associated one of the memory areas to be one of a valid memory area and an invalid memory area;
writing a current value to the invalid memory area;
erasing simultaneously a previously valid memory area and the associated nonvolatile control memory cell; and
programming simultaneously with the erasing step, the associated nonvolatile control memory cell for a memory area of the main areas to which information has previously been written so that the memory area can be recognized as the valid memory area.
According to the invention, the current value, preferably the counter reading of a binary counter, is programmed in nonvolatile form in a memory area provided for this purpose. The memory area has at least one associated control memory cell whose charge state identifies the memory area as a currently inactive or invalid memory area. A further memory area stores the previously valid value, that is to say the previous counter reading, with the associated control memory cell identifying this memory area as the valid memory area.
After the current value or counter reading has been written to the (still) invalid memory area, the (still) valid memory area is erased and, according to the invention, the charge state of the associated control memory cell is changed, for example erased, simultaneously, so that the memory area is now indicated as being the invalid memory area. Likewise simultaneously, the charge state of the control memory cell for the memory area to which information has just been written is also changed, for example programmed, so that this memory area is identified as being the memory area which is now valid.
Thus, in the case of the method according to the invention, only two erasing and programming operations are required for each change of memory area. Before the memory area to which information has newly been written is distinguished as being valid, the correctness of the written value can be checked in a known manner, in order to prevent manipulation. The memory areas advantageously contain the same amount of cells as the value has places or as the counter representing the value has counter places.
In one preferred circuit configuration that allows the method to be carried out, each control memory cell memory transistor has two selection transistors connected in series with it. The selection transistors connect the source and the drain connection of the memory transistor to ground and to a bit line to which a programming voltage can be applied, respectively. The gate connections of the selection transistors are thus interconnected in such a way that one memory transistor is erased when the other is programmed. In addition, the control gates of the memory transistors in the control memory cells are connected to the control gates of the memory transistors in the associated memory areas in such a way that erasing one memory area results in the associated control memory cell also being erased.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated circuit configuration, containing a memory. The memory includes at least two nonvolatile memory areas for storing currently valid values. The memory areas are formed of memory transistors having gate connections and drain connections. Nonvolatile control memory cells including a first control memory cell and a second control memory cell are provided. Each of the memory areas are connected to at least one of the control memory cells. The control memory cells have state
Greenberg Laurence A.
Le Vu A.
Lerner Herbert L.
Nguyen Tuan T.
Siemens Aktiengesellschaft
LandOfFree
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