Computer graphics processing and selective visual display system – Display driving control circuitry – Display power source
Reexamination Certificate
1999-01-21
2001-10-30
Mengistu, Amare (Department: 2778)
Computer graphics processing and selective visual display system
Display driving control circuitry
Display power source
C345S204000, C345S089000
Reexamination Certificate
active
06310616
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a voltage generating (output) circuit used as a drive source of a device for directly or indirectly driving a capacitive load; a common electrode drive circuit of a display device provided with the voltage generating circuit, for driving a common electrode in a display device; and a signal line drive circuit and a gray-scale (gradation) voltage generating circuit of a display device provided with the voltage generating circuit, for driving the signal lines in a display device.
2. Description of the Related Art
An active matrix liquid crystal display device of
FIG. 48
represents an example of the above-mentioned display device. This liquid crystal display device includes liquid crystal which is a display medium between two substrates
100
and
101
facing each other. Pixel electrodes
103
(P(i, j)) are arranged in a matrix on the liquid crystal side of the substrate
100
, and signal lines (data lines or source lines)
104
(S(
1
), S(
2
), . . . , S(i), . . . , S(N)) and scanning lines (gate lines)
105
(G(
1
), G(
2
), . . . , G(j), . . . , G(M)) are provided at the periphery of each pixel electrode
103
so as to cross each other. A thin film transistor (TFT)
102
(T(i, j)) is provided as a switching element in the vicinity of each crossing portion of the signal lines
104
and the scanning lines
105
. The TFT
102
is connected to the signal line
104
, the scanning line
105
, and the pixel electrode
103
so as to drive the pixel electrode
103
.
A common electrode
101
a
is provided on the liquid crystal side of the other substrate
101
. A capacitance of the liquid crystal contributing to a display is formed between the common electrode
101
a
and the pixel electrodes
103
.
A source driver (signal line drive circuit)
200
is connected to the signal lines
104
, and a gate driver
300
is connected to the scanning lines
105
. The source driver
200
supplies a voltage to the signal lines
104
; in the example shown in
FIG. 48
, a digital source driver to which a video signal is applied in a digital form is used. The source driver
200
and the gate driver
300
are provided with an output signal from a control circuit
600
. The control circuit
600
supplies a control signal POL to a gray-scale voltage generating circuit
400
and a common electrode drive circuit
500
. The gray-scale voltage generating circuit
400
outputs gray-scale voltages v
0
, v
1
, v
2
, and v
3
to the source driver
200
, and the common electrode drive circuit
500
outputs a common electrode voltage v
com
to the common electrode
101
a.
Hereinafter, the gray-scale voltage generating circuit
400
and the common electrode drive circuit
500
provided in the display device thus constructed will be as described.
FIG. 49
shows an example of a drive circuit as proposed in “Drive Circuit for Display Apparatus,” U.S. Pat. No. 5,402,142 to H. Okada et al. This drive circuit works as the gray-scale voltage generating circuit
400
as well as the common electrode drive circuit
500
. The drive circuit is provided with an operational amplifier OP
C
for generating the common electrode voltage v
com
, and operational amplifiers OP
0
to OP
3
for generating the gray-scale voltages v
0
to v
3
. Each inversion input terminal of the operational amplifiers OP
C
, OP
0
, and OP
1
is provided with the control signal POL. The control signal POL is inverted by an inverter INV and then input to each inversion input terminal of the operational amplifiers OP
2
and OP
3
. Each non-inversion input terminal of the operational amplifiers OP
c
and OP
0
to OP
3
is provided with an output from resistance type potential dividers PD
com
and PD
0
to PD
3
, respectively. The resistance dividers PD
com
and PD
0
to PD
3
respectively consist of two fixed resistors R
c1
and R
c2
, R
01
and R
02
, R
11
and R
12
, R
21
, and R
22
, and R
31
and R
32
. One terminal of each of the resistors R
c1
, R
01
, R
11
, R
21, and R
31
is connected to a power supply V
dd
at a positive electric potential; and each of the other terminals of the resistors R
c2
, R
02
, R
12
, R
22
, and R
32
is connected to a power supply V
ss
at a ground electric potential.
FIG. 50A
shows an example of an output waveform of the above-mentioned drive circuit. When the control signal POL is at a high level, the common electrode voltage v
com
and the gray-scale voltages v
0
to v
3
are output so that a voltage applied to a pixel has a positive polarity with respect to the common electrode (a time period in this state is referred to as “positive time period”). When the control signal POL is at a low level, the common electrode voltage v
com
and the gray-scale voltages v
0
to v
3
are output so that a voltage applied to a pixel has a negative polarity with respect to the common electrode (a time period in this state is referred to as “negative time period”). In either time period, the absolute value of an electric potential difference between the common electrode and the pixel electrode is set to be higher in the same order of the data value 0 to 3 (i.e., |v
0
−v
com
|<|v
1
−v
com
|<|v
2
−v
com
|<|v
3
−v
com
|).
The above relation represents a condition for driving a liquid crystal display body in a normally black mode. The above relation may be reversed when a liquid crystal display body is driven in a normally white mode.
FIG. 50B
shows an output in the case where the liquid crystal display body is driven in a normally white mode. It is not related to the present invention in which mode the liquid crystal display body is driven; therefore, in the following examples, either case (i.e., a normally black mode or a normally white mode) will be described. Unless otherwise stated, the level of a voltage refers to that in a positive time period.
FIGS. 50A and 50B
show waveforms in a line inversion in which the polarity of a voltage applied to a pixel is inverted per horizontal line (transverse line or row line).
The common electrode voltage v
com
and gray-scale voltages v
0
to v
3
oscillate in synchronization with the control signal POL based on a reference voltage v
M
(i.e., a voltage applied to each non-inversion input terminal) are output from the operational amplifiers OP
c
and OP
0
to OP
3
by appropriately setting the fixed resistors R
01
, R
02
, R
11
, R
12
, R
21
, R
22
, R
31
, and R
32
. As is understood from
FIG. 50A
, the voltages v
com
, v
0
, and v
1
have a phase opposite to that of the voltages v
2
and v
3
. The amplitude of these voltages are determined in terms of an amplification ratio of the operational amplifiers OP
c
and OP
0
to OP
3
.
FIG. 51
shows the gray-scale voltages v
0
to v
3
, based on the common electrode voltage v
com
which is applied to the common electrode
101
a
. As is understood from
FIG. 51
, when a certain pixel is selected by the gate driver
300
through the scanning lines
105
, the pixel electrode
103
is charged with an output (i.e., one of the gray-scale voltages v
0
to v
3
) from the source driver
200
connected to the selected pixel, and the difference between the electric potential at the pixel electrode
103
and that of the common electrode
101
a
facing the pixel electrode
103
with the liquid crystal layer sandwiched therebetween.
As described above, in the case where the common electrode
101
a
is driven with an A.C. voltage, there is an advantage that the amplitude of a voltage to be applied to a signal line for obtaining a predetermined voltage between the pixel electrode
103
and the common electrode
101
a
a can be decreased and a working voltage for the source driver
200
can be decreased (see Japanese Laid-Open Patent Publication No. 3-177890).
The gray-scale voltages v
0
to v
3
are supplied to the source driver
200
which is a signal line drive circuit.
FIG. 52
shows a circuit diagram showing the structure of the source driver
200
. Video signal data is composed of
Nishitani Tadatsugu
Okada Hisao
Takarada Takeshi
Yamamoto Yuji
Yanagi Toshihiro
Mengistu Amare
Nixon & Vanderhye P
Sharp Kabushiki Kaisha
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