Computer graphics processing and selective visual display system – Display peripheral interface input device – Cursor mark position control device
Reexamination Certificate
1997-10-14
2001-02-27
Cuchlinski, Jr., William A. (Department: 3661)
Computer graphics processing and selective visual display system
Display peripheral interface input device
Cursor mark position control device
C345S156000, C345S157000, C345S161000, C345S167000
Reexamination Certificate
active
06195084
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method for the production of semiconductor devices.
2. Description of the Prior Art
The process of producing a semiconductor integrated circuit includes the operation of forming a film on a semiconductor wafer and patterning the film by photolithography at several steps.
For the purpose of forming a plurality of identical semiconductor integrated circuits on one semiconductor wafer, the photolithography adopts the method of step and repeat reduction-type projection printing. The projection printing method utilizes a reticule having a plurality of identical circuit patterns arrayed adjacently thereon, to effect simultaneous exposure of a resist to the plurality of circuit patterns.
The semiconductor wafer, after having these semiconductor integrated circuits formed thereon, is divided into individual chips, each bearing one of the semiconductor integrated circuits.
However, as illustrated in
FIG. 1A
, since a semiconductor wafer
101
has a circular shape and, one unit circuit pattern forming area on a reticule
102
has a rectangular shape, a certain proportion of the circuit patterns
103
a
to
103
d
on the reticule
102
used during the exposure inevitably protrude from the semiconductor wafer
101
during the exposure (the hatched area in the diagram). The circuit patterns
103
d
which are formed near the circumference of the semiconductor wafer
101
and contain a missing portion will be referred to hereinafter as “rejectable circuit patterns” or “rejectable chips.”
Also, as the puddle developing method, inwhich a liquid developer is piled on a semiconductor wafer, is generally adopted as the means to develop an exposed resist, the circumferential region of the semiconductor wafer is insufficiently developed. This inevitably gives rise to abnormally shaped resist patterns.
When the abnormally shaped resist patterns such as this exist near the circumference edge of the semiconductor wafer, films which are patterned using this resist pattern as a mask, are also abnormally shaped. Problems can occur, for example during the formation of storage electrodes on DRAM, when a hydrofluoric acid treatment is done to remove the silicon oxide film from beneath a polycrystalline silicon film, which forms the storage electrode. The polycrystalline silicon that is not connected to the substrate in the abnormally patterned area floats off and becomes attached as a particle in the normal pattern area, forming a factor causing reduced yields.
As a way of removing such abnormal patterns, a method of projecting light onto the whole area destined to produce rejectable chips after the exposure may be adopted as disclose in JP 07142309A. This method, however, is not as effective in preventing the occurrence of abnormal patterns as expected because it produces no change in the fact that the development is insufficient in the area of rejectable chips.
To cope with this problem, a method has been adopted of omitting the projection of the circuit patterns
103
a
to
103
d
of the reticule
105
of
FIG. 1B
at the positions where the circuit patterns overlap the circumference edge of the semiconductor wafer
101
, i.e. the position which correspond to the hatched area of FIG.
1
A.
However if the exposure to light is omitted from the area in which the circumference edge of the semiconductor wafer overlaps at least one of the circuit patterns on the reticule, a wasted area of a width which covers one to three circuit patterns arises near the circumference edge of the semiconductor wafer. This causes a problem of lowered yield.
The practice of forming only one circuit pattern on a reticule and using this reticule for the purpose of exposure to light is also an option. However, this causes a large increase in the number of shots of light involved during the treatment of exposure to light, and inevitably results in a decrease in the throughput.
SUMMARY OF THE INVENTION
The object of this invention is to provide a method for the production of semiconductor devices, which incorporates therein a patterning step which is capable of repressing the occurrence of particles and also improves the throughput and the yield during the treatment of exposure to light.
In this invention, after a plurality of circuit patterns in a reticule (exposure mask) are projected onto a resist on a semiconductor wafer, with the exposure of the circuit patterns which overlap with the edge of the wafer being blocked by a blind, a separate mask is used to selectively expose the parts in the resist to which the edge of the blind was projected, and to remove these parts.
As a result, the exposure of the ineffective circuit patterns which overlap with the edge of the wafer is prevented, the formation of abnormal resist patterns which occurs around the circumference of a semiconductor wafer is avoided, and the occurrence of abnormal resist patterns which occur as a result of the blurred focus where the edge of the blinds are projected is also prevented. It is therefore possible to greatly suppress the occurrence of particles, which arise from these abnormal resist patterns.
Further, since only those of the plurality of circuit patterns formed in the reticule which do not overlap the edge of the semiconductor wafer are exposed to light, the number of available circuit patterns that are formed on the semiconductor wafer does not need to be reduced. As a result, the yield is improved because the number of available chips per semiconductor wafer is increased.
There is no reduction of throughput because the reticule to be used has a plurality of circuit patterns formed therein.
The reticule which is used for erasing the edge of a blind transferred to the resist may be formed in the same reticule that contains the circuit patterns, or may be formed as a separate entity.
When a plurality of circuit patterns are to be arranged repeatedly in a lengthwise and a crosswise direction in one reticule, this reticule is provided with lengthwise oblong or crosswise oblong light passing patterns for erasing the latent image or the edge of the blind in the resist. In this case, the aperture area of the lens can be effectively utilized by locating the light passing pattern in the area surrounding the circuit patterns area and near the center of the circuit patterns area.
Further, the lengthwise oblong light passing pattern is given a greater length than one side of a circuit pattern in the lengthwise direction, and the crosswise oblong light passing pattern given a greater length than another side of the circuit pattern in the crosswise direction. In this arrangement, it is possible to leave no space between the projections of lights on line of the latent image of the edge of the blind, when the part of the resist which was exposed at the edge of the blind is split into several parts for the exposure.
The available exposure area of the lens can be utilized to the utmost by positioning the light passing pattern close to the center of the circuit patterns area. The formulation of the program at the stage of designing the circuit patterns on the reticule is facilitated if the light passing pattern is symmetrical.
It becomes possible to obviate the necessity of changing reticules and avoid a decline in throughput arising from re-alignment, if the circuit patterns and the light passing patterns for the erasure of the latent image of the blind edge are formed on one and the same reticule.
REFERENCES:
patent: 4964075 (1990-10-01), Shaver et al.
patent: 5305449 (1994-04-01), Ulenas
patent: 5611040 (1997-03-01), Brewer et al.
patent: 5793972 (1998-08-01), Shane
patent: 5870080 (1999-02-01), Burnet et al.
patent: 5898424 (1999-04-01), Flannery
Cuchlinski Jr. William A.
Marc-Coleman Marthe Y.
Micron Electronics Inc.
Park & Vaughan LLP
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