Two bit partitioning circuit for a dynamic, programmed logic arr

Details Two bit partitioning circuit for a dynamic, programmed logic arr Two bit partitioning circuit for a dynamic, programmed logic arr

1975-09-25

1977-01-04

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307215, 307246, 307270, 307DIG1, 307DIG4, 307DIG5, H03K 1908, H03K 1934, H03K 1710, H03K 1756

Patent

active

040016013

ABSTRACT:
A two bit partitioning circuit for a dynamic programmed logic array which introduces two stages of delay in the signal path in one clock cycle, with minimum power dissipation. The circuit has two primary inputs and four outputs which serve as inputs to a bootstrap driver which produces an output signal to the programmed logic array. A basic path through the circuit consists of two stages, the first stage comprising two active devices (FET) and a first capacitive means, while the second stage comprises three active devices and a second capacitive means. The major portion of the capacitance of the second stage is provided by the capacitance of the bootstrap driver. The stages are dynamic with the discharge speed of the first stage being much faster than that of the second stage thereby enabling a signal to propagate through the two stages in one clock cycle, with the only power dissipation being that required to charge the two capacitive means.

REFERENCES:
patent: 3601627 (1971-08-01), Booher
patent: 3644904 (1972-02-01), Baker
patent: 3665473 (1972-05-01), Heimbigner
patent: 3778784 (1973-12-01), Karp et al.
patent: 3906464 (1975-09-01), Lattin
West, "Practical Circuit Design Using M.O.S."; Design Electronics, vol. 8, No. 6; 3/1971; pp. 30-32, 37-38.

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