Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
1996-09-18
2001-12-11
Paladini, Albert W. (Department: 2841)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C257S688000, C257S700000, C228S180210, C439S060000, C439S091000
Reexamination Certificate
active
06329607
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to components and methods used in mounting and connecting microelectronic elements such as semiconductor chips.
BACKGROUND OF THE INVENTION
Semiconductor chips and other microelectronic elements typically have contacts which must be connected to external circuitry, such as the circuitry of a supporting substrate or circuit panel. Various processes and components for making these connections have been provided heretofore. For example, in a wire bonded assembly the chip is physically mounted on a substrate and individual fine wires are connected between the contacts of the chips and contact pads on the substrate. In tape automated bonding or “TAB” processes, a dielectric supporting tape such as a thin foil of a polymer is provided with a hole slightly larger than the chip. An array of metallic leads is provided on one surface of the dielectric tape. These leads extend inwardly from around the hole so that an inner end of each lead projects inwardly beyond the edge of the hole. These ends are arranged side by side at spacings corresponding to the spacings of the contacts on the chip. The inner ends of the leads are bonded to the contacts on the chip, whereas outer ends of the leads are attached to contact pads on the substrate. In the “beam lead” process, the chip is provided with leads extending from contacts on the chip outwardly beyond the edges of the chip. The chip is positioned on the substrate so that the outer ends of the leads lie over the appropriate contact pads of the substrate and the leads are bonded to the contact pads.
The rapid evolution of the semiconductor art has created a need for progressively greater numbers of contacts and leads in a given amount of space. An individual chip may require hundreds or even thousands of contacts and leads. For example, a complex semiconductor chip in current practice may have rows of contacts spaced apart from one another at center to center distances of 0.5 mm or less. These distances are decreasing progressively with continued progress in the semiconductor art. With such closely spaced contacts, the leads connected to the chip contacts such as the wires in wire bonding and the leads used in the TAB and beam lead processes must be extremely fine structures, typically less than 0.1 mm wide. These fine structures are susceptible to damage and deformation during manufacture. Even minor deviation of a lead from its intended position during the bonding process can result in defects in the final assembly.
As disclosed, for example, in U.S. Pat. Nos. 5,489,749 and 5,536,909 and in PCT Published International Application WO 94/03036, published
3
February
1994
, all of which are incorporated by reference herein, a component for mounting a semiconductor chip may include a support structure such as a polymeric film defining one or more gaps and one or more leads extending across such gap. The supporting structure typically has terminals on it. Each lead has a connection section with a first end permanently secured to the supporting structure on one side of the gap and a second end remote from the first end. The first ends of the lead connection sections typically are connected to the terminals. The second end of each connection section may be releasably secured to the opposite side of the gap. For example, each lead may include a frangible section connecting the second end of the connection section to the support structure. Thus, each lead bridges across the gap in the support structure. The leads are maintained in the proper position and orientation so that when the connection component is juxtaposed with the chip, each lead is at or near the desired position relative to the associated contact on the chip. Each lead is then engaged by a bonding tool which enters the gap and forces each lead downwardly into engagement with the appropriate contact of the chip. Preferably, each lead is guided by the bonding tool during this operation. Because each lead is supported at both ends, the leads remain in position before the bonding process. When the leads are bonded to the contacts of the chip, the terminals on the supporting structure are electrically connected to the chip. Thus, the chip can be connected to external circuitry by attaching the terminals on the supporting structure to a larger substrate, as by solder bonding the terminals to the larger substrate. The bonded leads typically provide flexible interconnections between the contacts of the chip and the terminals and thus allow compensation for thermal expansion and contraction of the chip and substrate. Components and bonding methods as disclosed in the '749 and '909 patents and in the '036 International Publication provide rugged, compact and economical chip mountings, and offer numerous advantages. Still further improvements and enhancements to such chip mountings are disclosed in U.S. Pat. No. 5,398,863 and U.S. Pat. No. 5,491,302, the disclosures of which are hereby also incorporated by reference herein. Bonding tools useful in attaching leads according to the '794 patent and '036 publication and for other purposes are disclosed in U.S. Pat. No. 5,390,844, the disclosure of which is also incorporated by reference herein.
The connection sections of leads made in accordance with the aforementioned patents and publication most typically are made from metals such as copper, gold, platinum, nickel, aluminum, silver and alloys of these metals. Combinations of multiple metal layers may also be employed. The '749 and '909 patents also disclose the use of polymeric strips, such as polymeric strips formed integrally with the support structure, in the leads. Thus, the polymeric strips serve as part of the lead structure, along with one or metal layers. In certain embodiments disclosed in these patents, the frangible sections are formed by interrupting the metal layers. In these embodiments, the polymeric layer extends across the frangible section, so that the polymeric layer breaks when the end of the connection section is displaced downwardly into engagement with the chip. As further disclosed in these patents, the polymeric strips can be employed in cantilevered leads, i.e., in leads which are not supported at both ends prior to bonding in accordance with the preferred embodiments of the patents. Still other structures taught in these patents provide the polymeric strip as a reinforcement only adjacent the first end of the lead connection section, i.e., only where the lead joins the support structure, so as to alleviate stress concentration at this point. The remainder of the lead is composed only of the metal layers.
Other lead structures are disclosed in U.S. Pat. No. 5,518,964, the disclosure of which is also incorporated by reference herein. As shown in certain embodiments of the '964 patent, a microelectronic connection component may include a dielectric sheet having an array of elongated, striplike leads. Each lead may have a terminal end permanently fastened to the sheet and a tip end detachably connected to the sheet. In use, the sheet can be juxtaposed with a microelectronic element such as a chip or an entire wafer. The tip ends of the leads are bonded to the contacts on the chip while the tip ends remain attached to the sheet. After bonding, the sheet and the microelectronic element are moved away from one another, thereby detaching the tip ends from the sheet and bending the leads away from the sheet. This leaves the leads in a vertically extensive, flexible configuration.
Despite these improvements, still further improvements would be desirable. Thus, improvements in the structure of polymer reinforced leads to facilitate fabrication of such leads and to facilitate the bonding process would be desirable.
It also would be desirable to provide lead designs which offer even better resistance to the respected flexure encountered during operation, and which can provide good resistance to such failure even when formed with relatively brittle, fatigue-prone metals.
Moreover, the electric
Fjelstad Joseph
Smith John W.
Lerner David Littenberg Krumholz & Mentlik LLP
Paladini Albert W.
Tessera Inc.
LandOfFree
Microelectronic lead structures with dielectric layers does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Microelectronic lead structures with dielectric layers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Microelectronic lead structures with dielectric layers will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2563856