Structure of semiconductor device

Details Structure of semiconductor device Structure of semiconductor device

1998-08-13

2001-05-15

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making passive device

Resistor

C438S241000

Reexamination Certificate

active

06232195

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device structure, and more particularly, to the structure of a semiconductor device in which an nMOS thin film transistor is utilized as an access transistor in a static random access memory (SRAM), thereby reducing cell size and improving low Vcc characteristics.
Generally, in an SRAM, a refresh operation is unnecessary and operation timing of the memory can be easily performed. Thus, the SRAM can be made to have the same access time and cycle time as a microcomputer. Further, the SRAM can be made to operate at high speed comparable to that of a bipolar RAM.
However, as cell capacitance increases, it becomes difficult to decrease power consumption while maintaining the high speed operation in an nMOS SRAM.
Accordingly, a manufacturing process for fabricating the SRAM becomes complex because several different gate threshold voltages are required. Further, an operation margin must be reduced while manufacturing costs continue to increase.
Hereinafter, the structure of a conventional semiconductor device will be described with the reference to the attached drawings.
FIG. 1
is a schematic of a conventional SRAM cell, and
FIG. 2
is a cross-sectional view showing a portion of a semiconductor device illustrated in FIG.
1
.
In general, a MOS SRAM cell incorporates a flip-flop having a high-resistance load, as shown in FIG.
1
. The flip flop includes two cross-coupled invertors respectively consisting of transistors TR
1
and TR
2
and associated load elements of R
1
and R
2
. Further, nMOS transistors TR
3
and TR
4
are connected to a data line, and their gates are connected to a word line.
If the word line is at a high level, transistors TR
3
and TR
4
are turned on, thereby electrically connecting the basic cell to a data line B/L. If TR
1
is off and TR
2
is on, a data line B/L is set to a low level because current flows in the memory cell through TR
4
. Data line B/L, however, is charged up through TR
3
, without a current path to ground. Thus, this becomes a high level.
Conventionally, transistors TR
1
, TR
2
, TR
3
, and TR
4
are utilized as bulk transistors.
A semiconductor device structure used in the above-described circuit will now be described.
As shown in
FIG. 2
, a field oxide film
2
is formed on a predetermined region of a semiconductor substrate
1
. An access transistor gate electrode
3
and a drive transistor gate electrode
4
are spaced by a uniform distance on a semiconductor substrate
1
. On the entire surface of the resultant structure, an insulating film
5
is formed having a contact hole exposing a portion of gate electrode
4
, serving as the gate of a driver transistor. A load resistor layer
6
is formed electrically connected to drive transistor gate electrode
4
. A poly-s layer
7
for use as a Vss line is provided between load layer
6
and drive transistor gate electrode
4
, but insulated from each other. A metal line
9
is connected to a source impurity region
8
on one side of access transistor gate electrode
3
. Access transistor gate electrode
3
corresponds to the gate electrode of TR
3
in
FIG. 1
, and drive transistor gate electrode
4
corresponds to the gate electrode of TR
2
in FIG.
1
. Further, load resistor layer
6
formed in contact with drive transistor gate electrode
4
corresponds to load resistor R
1
In FIG.
1
.
A method of manufacturing the conventional semiconductor device having the aforementioned structure is as follows.
To begin with, as shown in
FIG. 3
a
, a first polysilicon layer, doped using POLI
3
, is deposited on the entire surface of a semiconductor substrate
11
on which a field oxide film was previously formed.
Then, after coating a photoresist film (not shown) on the first polysilicon layer, an access transistor gate electrode region and driver transistor gate electrode region are defined. Using photolithography and etching processes, an unnecessary portion of the first polysilicon layer is selectively removed, thereby forming access transistor gate electrode
12
and drive transistor gate electrode
13
.
Using access transistor gate electrode
12
as a mask, a low concentration n-type impurity ion is implanted to form LDD regions. Then, using a gate sidewall as a mask, a high-concentration n-type impurity ion is implanted to thereby form source/drain impurity regions
14
and
14
a.
At this time, as shown in
FIG. 2
, portion A, i.e., source/drain impurity region
8
a
at the boundary of field oxide film
2
beneath drive transistor gate electrode
4
and an active region are formed due to the diffusion of phosphorous from the POLI
3
doping.
As shown in
FIG. 3
b
, a first oxide film
15
and a second polysilicon layer are successively formed on the entire surface of semiconductor substrate
11
including access transistor gate electrode
12
and drive transistor gate electrode
13
. After coating a photoresist film (not shown) on the second polysilicon, a Vss line is defined. After patterning using photolithography and etching processes, the second polysilicon is selectively removed, thereby forming a Vss line
16
.
As shown in
FIG. 3
c
, a second oxide film
17
is deposited on the entire surface of first oxide film
15
including Vss line
16
. Second and first oxide films
17
and
15
, respectively, are selectively removed to create a contact hole exposing part of drive transistor gate electrode
13
.
A third polysilicon is deposited in contact with driver transistor gate electrode
13
. The third polysilicon is then patterned to form a load resistor layer
18
.
As shown in
FIG. 3
d
, planarizing oxide film
19
is deposited on the entire surface of second oxide film
15
including load resistor layer
18
.
After forming a contact hole so as to expose source impurity region
14
of the access transistor, a metal layer
20
is deposited, thereby completing the manufacturing process of the conventional semiconductor device.
However, in such structure of the conventional semiconductor device, the access transistor and drive transistor are realized as bulk transistors. Thus, the resulting cell size is increased. Further, speed is decreased due to the junction capacitance at the interface of the substrate and the n-type impurity regions. Further, the device suffers from poor low Vcc characteristics due to the bulk effect.
SUMMARY OF THE INVENTION
In order to solve the aforementioned problems, it is an object of the present invention to provide a structure of a semiconductor device in which the access transistor includes an nMOS thin-film transistor, thereby decreasing cell size and junction capacitance and improving low Vcc characteristics.
To accomplish the above object, in an SRAM including a drive transistor, an access transistor and a load resistor, there is provided a semiconductor device structure comprising a semiconductor substrate; a drive transistor gate electrode formed on the semiconductor substrate, with a first gate insulating film interposed therebetween; a first impurity region formed on the substrate on opposite sides of the drive transistor gate electrode; an insulating film formed on the surface of the substrate having a contact hole overlying the gate electrode of the drive transistor, a semiconductor layer connected to the gate electrode of the drive transistor through the contact hole and formed on the insulating film; a second gate electrode of the access transistor formed on the second gate insulating film; and a second impurity region formed on the semiconductor layer on opposite sides of the gate electrode of access transistor T
3
.


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patent: 5395784 (1995-03-01), Lu et al.
patent: 5486717 (1996-01-01), Kokubo et al.
patent: 5491654 (1996-02-01), Azuma
patent: 5506802 (1996-04-01), Kiyono
patent: 5578854 (1996-11-01), Chen et al.
patent: 59-130459 (1984-07-01), None
High Reliability and High Performance 0.35 &mgr;m Gate-Inverted TFT's for 16Mbit SRAM Applications Using Self-Aligned LDD Structures, C. T. Liu, IEDM 823-826 (De

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