Structure of a flash memory device

Details Structure of a flash memory device Structure of a flash memory device

2000-03-24

2001-07-17

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185140, C365S185010, C257S315000, C257S316000, C257S382000

Reexamination Certificate

active

06262917

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88118300, filed Oct. 22, 1999.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a structure of a flash memory device. More particularly, the present invention relates to a structure of a split-gate flash memory device.
2. Description of the Related Art
In general, the conventional structure of an erasable programmable read-only memory (EPROM) device is similar to that of the N-type metal-oxide-semiconductor (MOS), wherein the gate structure is the stacked gate type, comprising a polysilicon floating gate for charge storage and a control gate to control the storage and retrieval of information. Thus a typical EPROM unit comprises two gates, a floating gate and the underlying control gate. The control gate is connected to the word line, while the floating gate is maintained in a “floating” condition and has no connection with the external circuits. At present, the most popular type of flash memory device has been developed by Intel Corporation, in which the erasure operation can be conducted “block by block”, and the erasure speed is fast. The erasure operation is completed in 1 to 2 seconds, greatly reducing the time and the cost of operation. The traditional stacked gate structure of the flash memory device, wherein the floating gate and the control gate are stacked on each other, often result in the problem of an over-erasure during the flash-memory device erasure operation.
To resolve the over-erasure problem in the traditional stacked gate structure of a flash memory device, a split gate flash memory device is being developed.
FIG. 1
is a schematic, cross-sectional view of a split-gate flash-memory device according to the prior art. The structure of the split-gate flash memory device includes a substrate
100
, comprising a source region
102
a
and a drain region
102
b.
On the substrate
100
is a gate oxide layer
104
, wherein a floating gate
106
, a dielectric layer
108
and a control gate
110
are on the gate oxide layer
104
.
The operation conditions of a conventional split-gate flash-memory device are summarized in Table 1.
TABLE 1
Operation Conditions of a Conventional Split-Gate
Flash-Memory Device.
Bit Line
Source
Operations
Control Gate
(Drain Region)
Region
Substrate
Programming
8-12 V
3-8 V
GND
GND
Erasure
GND
GND
GND
>15 V
Reading
Vcc
1-2 V
GND
GND
In a split gate flash memory device, the control gate
110
and the floating gate
106
are not completely stacked on each other, the problem of an excessive erasure as in the conventional stacked gate is thereby obviated. As the device dimensions are continuously being reduced, the distance between the source region
102
a
and the drain region
102
b,
however, also decreases. A short channel between the source region
102
a
and the drain region
102
b
is results, easily leading to the punch through effect. The dimensions of a split-gate flash-memory device, as a result, cannot be scaled-down.
SUMMARY OF THE INVENTION
Based on the foregoing,
the present version of the current invention provides a structure of a flash memory device, which includes a substrate, a gate oxide layer, a floating gate, a source region, a drain region, a dielectric layer and a control gate, wherein the substrate comprises a trench. The gate oxide layer is situated on the substrate next to the trench and the floating gate is located on the gate oxide layer. The source region is located in the substrate at the bottom of the trench and the drain region is located on a side of the floating gate. The dielectric layer on the substrate conformally covers the floating gate, the gate oxide layer and the trench. A control gate is also located on the dielectric layer. Additionally, the trench is about 0.1 micron to 1 micron deep. The source region formed at the bottom of the trenches in the substrate, the floating gate, the drain region and another floating gate form an alternating structure.
Since the depth of the trench is about equal to the channel length of the split gate transistor, the channel length of the split gate transistor will not be affected by the shrinkage of the device dimensions because the source region is located deep in the substrate at the bottom of the trench. The punch through effect due to a reduction of the device dimension in the conventional practice is thus prevented.
Furthermore, the source region and the drain region are formed in the substrate after the formation of the floating gate; the fabrication of the floating gate thus has a greater processing window.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


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patent: 6066880 (2000-05-01), Kusunoki
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