Method of fabricating shallow trench isolation structure

Details Method of fabricating shallow trench isolation structure Method of fabricating shallow trench isolation structure

1999-03-08

2001-05-08

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

C438S296000, C438S435000

Reexamination Certificate

active

06228742

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor fabricating method. More particularly, the present invention relates to a method of fabricating an isolation region.
2. Description of the Related Art
An isolation region is formed in an integrated circuit for the purpose of separating neighboring device regions of a substrate and preventing the carriers from penetrating through the substrate to neighboring devices. In a dynamic random access memory (DRAM) device, for example, the field effect transistors (FETs) are isolated from each other by isolation regions in order to prevent current leakage among the FETs. Conventionally, local oxidation of silicon (LOCOS) technique is widely utilized in the semiconductor industry to provide isolation regions among the various devices in the substrate. Since the LOCOS technique has been used for quite a period of time, it is one of the most reliable and low-cost method for fabricating the device isolation regions. However, there are still some difficulties in the LOCOS process. These include internal stress generation and bird's beak encroachment. For a highly integrated device, the problem of bird's beak encroachment by the isolation regions is especially difficult to avoid. Thus the isolation regions cannot effectively isolate devices.
Shallow trench isolation (STI) technique is the other conventional method of forming isolation regions. An STI structure is formed by first anisotropically etching to form a trench in the substrate, and then depositing oxide in the trench to form an isolation region. Since an STI structure is scaleable and has no bird's beak encroachment problem as found in the conventional LOCOS technique, it has become widely used for forming sub-micron CMOS circuits.
However, some drawbacks still occur in the conventional STI structure. In the conventional STI fabrication process, a silicon oxide layer is formed to fill a trench after a liner layer is formed on the trench. A densification step is first performed at a high temperature and then a chemical-mechanical polishing step is performed to remove a portion of the silicon oxide. Or, the chemical-mechanical polishing step can be first performed and then the densification step is carried out. However, both of the above procedures form defects during the densification step. Because of the thermal expansion coefficient difference between the silicon substrate and the silicon oxide, the defects, such as defect lines, easily form in the substrate. Dislocation, which is one kind of defect line, commonly occurs. Once the dislocation extends into the source/drain region, dopants in the source/drain region easily diffuse along the dislocation. Thus, current leakage and bridging effects are likely to occur. The device quality thus is degraded. In a highly integrated circuit, the foregoing drawbacks become significantly serious and cause device failure, which degrades the product quality.
SUMMARY OF THE INVENTION
The invention provides a method of fabricating a shallow trench isolation structure. A mask layer is formed on the substrate. The mask layer and the substrate are patterned to form trenches in the substrate. The trenches comprise a smallest trench. A first isolation layer is formed on the mask layer to fill partially the trenches. A densification step is performed. A second isolation layer is formed on the first isolation layer to fill the trench. The first isolation layer and the second isolation layer are removed until the mask layer is exposed. The mask layer is removed.
In the step of forming the first isolation layer, because the trench is not fully filled, the trench opening is formed in the first isolation layer. In this manner, the stress, which is caused by the difference in thermal expansion coefficient between substrate and the first isolation layer, is released through the trench opening. The defect formation, the current leakage, and the bridging effect do not occur. The device failures do not happen, either. The product quality thus is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5796949 (1999-11-01), Chen
patent: 5843820 (1998-12-01), Lu
patent: 5918131 (1999-06-01), Hsu et al.
patent: 6097076 (2000-08-01), Gonzalez et al.

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