Computer graphics processing and selective visual display system – Display driving control circuitry – Display power source
Reexamination Certificate
1998-10-21
2001-05-22
Shalwala, Bipin (Department: 2673)
Computer graphics processing and selective visual display system
Display driving control circuitry
Display power source
C345S098000, C345S204000
Reexamination Certificate
active
06236393
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an interface circuit which interfaces a plurality of digital input signals having a small amplitude each by using comparators and shifts levels of the inputted digital input signals by using the comparators so that the digital signals are amplified, and particularly relates to an interface circuit which is installed inside a liquid crystal driving circuit and ensures suppression of EMI (electromagnetic interference: a generic term for discharge phenomena such as electromagnetic disturbance and interference with respect to outside) noise, as well as relates to the liquid crystal driving circuit incorporating the interface circuit.
BACKGROUND OF THE INVENTION
The following description will explain a conventional TFT (thin film transistor) -LCD (liquid crystal display) module, while referring to FIG.
40
. Here, “module” refers to an independent unit which satisfies requirements such that only by combining a plurality of the modules, a grand system such as a TV set or a personal computer can be formed.
A TFT-LCD module
501
is equipped with a controller
510
, a liquid crystal driving power source circuit
520
, a gate driver group (gate electrode driving circuit)
530
, a source driver group (source electrode driving circuit)
540
, and a liquid crystal panel
550
, as shown in FIG.
40
.
According to a synchronization signal supplied from outside (from a host system), the controller
510
controls production of a scanning pulse by the gate driver group
530
and performs timing control of an Nbit display data signal and a driving control signal by the source driver group
540
. The liquid crystal power source circuit
520
receives power from an external power source and supplies power to the gate driver group
530
and the source driver group
540
, as well as to a common electrode.
The gate driver group
530
is composed of an “m” number of gate drivers G
1
through Gm, and the gate drivers G
1
through Gm are multi-output drivers for driving gate bus lines (a plurality of the same are provided horizontally as viewed in
FIG. 41
) of the liquid crystal panel
550
, and are generally referred to as gate drivers. Each gate driver is, though not shown in the figure, composed of (1) films called as tape carriers made of copper film wires which are laid at fine intervals on an insulating film so as to connect input/output terminals of an LSI chip with electrodes of other constituent parts, respectively, and (2) sealing resin for fixing and dehumidifying the LSI chip.
Likewise, the source driver group
540
is composed of an “n” number of source drivers S
1
through Sn. The source drivers SI through Sn are multi-output drivers for driving source bus lines (a plurality of the same are provided vertically as viewed in
FIG. 41
) of the liquid crystal panel
550
, and are generally referred to as source drivers. Each source driver is, though not shown in the figure, composed of (1) films called as tape carriers made of copper film wires which are laid at fine intervals on an insulating film so as to connect input/output terminals of an LSI chip with electrodes of other constituent parts, respectively, and (2) sealing resin for fixing and dehumidifying the LSI chip.
The liquid crystal panel
550
, as shown in
FIG. 41
, can be plotted into an equivalent circuit diagram of a TFT liquid crystal panel. In the liquid crystal panel
550
, a plurality of TFTs are provided in a matrix form, and each TFT is connected with a display electrode which is formed so as to correspond to each pixel. Further, the common electrode is formed so as to face each display electrode. The common electrode is an electrode commonly corresponding to all the pixels.
When a positive voltage is applied to the gate electrode of the TFT (usually supplied from the gate driver), the TFT is turned on. In accordance with a voltage applied to the source bus line, a liquid crystal load capacitor formed between the display electrode and the common electrode is charged.
When a negative voltage is applied to the gate electrode, the TFT is turned off, and a voltage applied at the time is maintained by the liquid crystal load capacitor between the display electrode and the common electrode.
By controlling a gate voltage in a state in which an appropriate voltage is applied to the source electrode (usually supplied from the source driver), a desired voltage can be maintained by the pixel. Transmittance of the liquid crystal is varied in accordance with the voltage thus maintained, whereby images are displayed. To be more specific, as shown in
FIG. 42
, the liquid crystal whose transmittance has varied is backlighted, and light having passed through the liquid crystal is projected on color filters, whereby images are displayed.
The following description will explain the gate drivers G
1
through Gm constituting the gate driver group
530
, while referring to FIG.
43
. Since the gate drivers G
1
through Gm have the same arrangement,
FIG. 43
is a schematic block diagram of one gate driver LSI chip.
The gate driver LSI chip is provided with a shift register circuit
561
, a level shifter circuit
562
, and an output circuit
563
. The functions of the blocks will be explained below.
The shift register circuit
561
performs a shifting operation in accordance with a horizontal synchronization signal SPD in response to a vertical synchronization signal CLD, and outputs a selection pulse for selecting, from among the pixels of the liquid crystal panel, a pixel to be driven by a voltage outputted from the source driver group
540
.
The level shifter circuit
562
shifts a level of the selection pulse to a voltage level required for turning on/off TFTs, and a signal thus converted is sent to the output circuit
563
. The output circuit
563
amplifies the signal thus inputted thereto, by using an output buffer circuit installed therein, and outputs the amplified signal through an output terminal. Outputs OP
1
through OPn from the output circuit
563
are signals in a pulse form, and are hereinafter referred to as gate pulses.
Signal timings of the vertical synchronization signal CLD, the horizontal synchronization signal SPD, and the outputs OP
1
through OPn are shown in
FIG. 44
which explains the present invention.
The following description will explain the source drivers S
1
through Sn constituting the source driver group
540
, while referring to FIG.
45
.
FIG. 45
is a schematic block diagram showing one of the source driver LSI chips which constitute the source drivers S
1
through Sn, respectively. A block diagram of an arrangement for display with
64
scales of color gradation is shown here.
The source driver LSI chip is composed of a shift register circuit
571
, an input latch circuit
572
, a sampling memory circuit
573
, a holding memory circuit
574
, a reference voltage producing circuit
575
, a DA converter circuit
576
, and an output circuit
577
. The functions of the blocks are explained below.
The shift register circuit
571
performs a shifting operation in response to a start pulse signal SPI of the source driver in accordance with an input clock signal CK, and selects a bit for sampling data. Here, a start pulse signal SPO (cascade output signal) is outputted from a final stage of the shift register circuit
571
to an LSI chip of the subsequent stage.
Therefore, the start pulse signal SPI is supplied from outside only to the source driver S
1
among the source drivers S
1
through Sn installed in the liquid crystal panel
550
. Regarding each of the other source drivers, the cascade output signal SPO taken out of the final stage of the previous shift register circuit
571
is inputted as the start pulse signal.
FIG. 46
shows an example of a liquid crystal panel
550
equipped with four source drivers.
The input latch circuit
572
temporarily latches an input display data signal DATA (6 bits per each of R, G, and B), and thereafter, sends it to the sampling memory circuit
573
.
The sampling memory circuit
573
samples the data inputted ther
Ogawa Yoshinori
Tamai Shigeki
Watanabe Takuya
Nixon & Vanderhye PC
Osorio Ricardo
Shalwala Bipin
Sharp Kabushiki Kaisha
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