Non-volatile semiconductor memory device

Details Non-volatile semiconductor memory device Non-volatile semiconductor memory device

1999-09-29

2001-02-13

Elms, Richard (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185170, C365S185180, C365S185190

Reexamination Certificate

active

06188611

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device (EEPROM) capable of electrically rewriting data, which device is constituted by memory cells each having a MOS transistor structure having a charge storage layer and a control gate, and more particularly, to an EEPROM for writing/erasing data in/from each memory cell using a tunnel current.
2. Description or the Related Art
In the field of EEPROMs, a memory cell of a MOS transistor structure having a charge storage layer (floating gate) and a control gate is widely used, and there is a growing trend toward higher integration densities. This memory cell is capable of electrically writing data by exchanging charges between the floating gate and the semiconductor substrate.
In a device of this type, when a data erase operation is to be performed, a high electric field is applied to the tunnel oxide film of each memory cell between the floating gate and the semiconductor, posing problems in terms of dielectric breakdown and leakage current. In a data write operation, a high electric field is applied to the tunnel oxide film, and hence a great stress is applied thereto. For this reason, the tunnel oxide film of each memory cell deteriorates after the device is used for a predetermined period of time. This deterioration in the tunnel oxide film will reduce the resistance of cell data to a stress acting on each cell in a cell data read operation, and shorten the service life of cell data.
As one of the above EEPROMs, a NAND-type EEPROM which allows a high integration density is known. In a NAND-type EEPROM, a plurality of memory cells are connected in series such that the respective adjacent memory cells share sources and drains. These memory cells are connected, as a unit, to a bit line. Each memory cell generally has an FET structure in which a charge storage layer and a control gate are stacked on each other. A memory cell array is integrally formed in a p-type well formed in a p- or n-type substrate.
The drain and source sides of a NAND cell are respectively connected to a bit line and a source line (reference potential line) via selection gates. The control gates of the respective memory cells are continuously connected to each other in the row direction to constitute a word line. In general, a set of cells connected to the same word line is called a page, and a set of pages between a pair of selection gates on the drain and source sides is called a NAND block or simply a block. In general, one block is the minimum unit which can be independently erased.
The NAND-type EEPROM is operated as follows.
A data erase operation is performed with respect to the memory cells in one NAND block at once. All the control gates of a selected NAND block are set at V
SS
, and a high voltage V
pp
(e.g., 20 V) is applied to the p-type well and the n-type substrate. With this operation, electrons are discharged from the floating gates of all the memory cells, and the threshold value of each memory cell shifts in the negative-value direction (normally, this state is defined as a “1” state). A chip erase operation is performed by setting all the NAND blocks in a selected state.
A data write operation is sequentially performed from the memory cell located farthest from the bit line. A high voltage V
pp
(e.g., 20 V) is applied to a selected control gate in a NAND block, and an intermediate potential V
M
(e.g., 10 V) is applied to the remaining non-selected control gates. A potential V
SS
or V
bitH
(8 V) is applied to the bit line in accordance with data. When the potential V
SS
is applied to the bit line (“0” write operation), the potential is transferred to the selected memory cell, and electrons are injected into the floating gate. As a result, the threshold value of the selected memory cell shifts in the positive-value direction (normally this state is defined as a “0” state). When the potential V
bitH
is applied to the bit line (“1” write operation), since no electrons are injected into the memory cell, the threshold value of the memory cell does not change and remains negative. The potential V
M
is applied to the drain-side selection gate to transfer the bit line potential.
A data read operation is performed as follows. The control gate of a selected memory cell in a NAND block is set at V
SS
, and the remaining control gates and the selection gates are set at V
CC
. In this state, it is checked whether a current flows in the selected memory cell. The readout data is latched in a sense amplifier/data latch circuit.
A write verify cycle will be described below.
After write data is input, a set voltage (e.g., 20 V) is applied to selected control gates for a set time (e.g., 40 &mgr;sec), Thereafter, a read operation is performed to confirm the completion of the write operation. If there are any memory cells which have undergone an insufficient write operation, a write operation is performed again with respect to these memory cells by applying a voltage of 20 V thereto for 40 &mgr;sec. At this time, with respect to memory cells which have undergone a sufficient write operation, the potential V
bitH
is applied to the bit line to prevent further electron injection. That is, the write operation with a voltage of 20 V and a writing time of 40 &mgr;sec is repeated until the data is completely written in all the memory cells.
Table 1 shows potentials at the respective portions in this case.
TABLE 1
Number of
Times of
Write
First
Second
Third
Fourth
Fifth
Operations
Time
Time
Time
Time
Time
(V
bitH
)
bit line
8V
8V
8V
8V
8V
“1”
bit line
V
SS
V
SS
V
SS
V
SS
8V
“0”
(V
M
)
SG
D
10V
10V
10V
10V
10V
(V
M
)
CG
1
to CG
7
10V
10V
10V
10V
10V
(V
PP
)
CG
8
20V
20V
20V
20V
20V
(selected)
CG
S
V
SS
V
SS
V
SS
V
SS
V
SS
In the above write method of verifying data in units of blocks (or chips), a method of writing data while increasing the voltage (high voltage V
pp
) applied to each control gate so as to shorten the programming time is known (to be referred to as a chip-by-chip verify voltage increasing method hereinafter).
This write method will be described below with reference to FIG.
1
. In the method, a program is written by the following procedure.
There are variations in process and threshold value among the respective memory cells. For example, in this case, the threshold value of a memory cell having the minimum threshold value (i.e., a hardest cell M
2
to write thereto) is set to be V
th
=−4 V (A
0
in FIG.
1
); a memory cell having the maximum threshold value (i.e., an easiest memory cell M
1
to write thereto) is set to be V
th
=−1 V (B
0
in FIG.
1
); and the threshold value of a memory cell in which “0” is written is set to fall within the range of 0.5 V to 2 V.
A page (or a chip) is selected first.
The potential V
SS
(e.g., 0 V) for “0” write operation or the potential V
bitH
(e.g., 10 V) for “0” write operation is applied to the bit line connected to each memory cell of the selected page in accordance with data to be written.
Thereafter, the first write operation is performed by applying the high voltage V
pp
(e.g., 18.5 V) to each selected word line (i.e., the control gate of each selected memory cell).
Upon completion of the first write operation, it is checked whether the threshold value V
th
of each memory cell has reached a completion determination level (verify operation). At this time, the threshold value V
th
of the memory cell M
1
is 0 V (B
1
), and the threshold value V
th
of the memory cell M
2
is −3 V (A
1
).
Since both the threshold values V
th
of the memory cells M
1
and M
2
are lower than a predetermined value, it is determined that the write processing is not completed. As a result, a constant voltage V
pp
(e.g., 19.5 V) higher than the voltage applied in the first write operation is applied to each selected word line, thus performing the second write operation. With the second write operation, the threshold value V
th
of the memory cell M
1
becomes 3 V (B
3
), and hence falls within the predetermined

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