Synchronous semiconductor memory device capable of selecting...

Details Synchronous semiconductor memory device capable of selecting... Synchronous semiconductor memory device capable of selecting...

2000-11-30

2001-12-25

Ho, Hoai V. (Department: 2818)

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

C365S230090, C365S233100, C365S236000

Reexamination Certificate

active

06333892

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a synchronous semiconductor memory device, and particularly to a configuration of column-selection-related circuitry for achieving a high-speed column selecting operation. More specifically, the present invention relates to a configuration of circuitry related to internal column addresses in the synchronous semiconductor memory device.
2. Description of the Background Art
FIG. 44
is a schematic diagram showing an entire structure of a conventional synchronous semiconductor memory device. Referring to
FIG. 44
, the conventional synchronous semiconductor memory device includes a memory cell array
900
having a plurality of memory cells MCs arranged in rows and columns. In memory cell array
900
, word lines WLs corresponding to respective rows of the memory cells and bit line pairs BLPs corresponding to respective columns of the memory cells are arranged.
The synchronous semiconductor memory device further includes: a clock input buffer
902
buffering an externally supplied clock signal extCLK to generate an internal clock signal CLK; a command decoder
904
determining the states of control signals that are externally supplied synchronously with internal clock signal CLK, i.e., a chip select signal /CS, a row address strobe signal /RAS, a column address strobe signal /CAS, and a write enable signal /WE, and generating an operation mode instruction signal indicating an operation mode according to the result of the determination; a control circuit
906
generating (activating) various control signals for performing the operation mode designated by the operation mode instruction signal from command decoder
904
; an internal address generating circuit
908
taking in an externally supplied address signal ADD in synchronization with internal clock signal CLK, passing the address signal according to a signal from command decoder
904
, and latching the address signal under the control of control circuit
906
to generate an internal row/column address signal; a row selecting circuit
910
for driving a word line corresponding to an addressed row of memory cell array
900
to a selected state according to the internal row address signal from internal address generating circuit
908
under the control of control circuit
906
; and a column selecting circuit
912
for selecting an addressed column of memory cell array
900
according to the internal column address signal from internal address generating circuit
908
under the control of control circuit
906
.
Command decoder
904
detects the states of chip select signal /CS, row address strobe signal /RAS, column address strobe signal /CAS, and write enable signal /WE at rising of clock signal CLK and determines the designated operation mode based on the detected states. The combination of the states of these control signals is referred to as “command”. Command decoder
904
thus decodes a command to generate an operation mode instruction signal indicating the designated operation mode.
Row selecting circuit
910
includes a decode circuit decoding the internal row address signal from internal address generating circuit
908
to generate a row selection signal, and a word line drive circuit driving a word line corresponding to a selected row to a selected state according to the row selection signal. Column selecting circuit
912
includes a column decode circuit (which may include a predecoder) decoding the internal column address signal from internal address generating circuit
908
, and a column selection gate corresponding to each column of memory cell array
900
for selecting a corresponding column and coupling the column to an internal data bus according to a column selection signal from the column decode circuit.
The synchronous semiconductor memory device further includes a read/write circuit
914
supplying/receiving data to/from a selected memory cell via column selecting circuit
912
synchronously with internal clock signal CLK under the control of control circuit
906
, and an input/output circuit
916
operating under control of control circuit
906
for communicating data between read/write circuit
914
and an external unit.
Referring to the timing chart illustrated in
FIG. 45
, an operation of the synchronous semiconductor memory device shown in
FIG. 44
is briefly described.
An active command ACT is supplied in clock cycle #a. The active command is issued by setting chip select signal /CS and row address strobe signal /RAS to a logical low or L level, and setting column address strobe signal /CAS and write enable signal /WE to a logical high or H level. When active command ACT is supplied, command decoder
904
decodes the command, drives an array activation instruction signal &phgr;act into an active state, and supplies it to control circuit
906
. Control circuit
906
activates row selecting circuit
910
according to array activation instruction signal &phgr;act, and causes internal address generating circuit
908
to generate an internal row address signal.
Internal address generating circuit
908
takes in external address signal ADD synchronously with rising of clock signal CLK, latches the external address signal according to array activation instruction signal tact from command decoder
904
, and generates an internal row address signal under the control of control circuit
906
. Row selecting circuit
910
then drives an addressed row of memory cell array
906
to a selected state according to the internal row address signal from internal address generating circuit
908
. When row selecting circuit
910
operated, data of memory cells of one row connected to a selected row (selected word line) WL is amplified to be latched by a sense amplifier (not shown) under the control of control circuit
906
.
In clock cycle #d, a read command RD is supplied. Read command RD is issued by setting chip select signal /CS and column address strobe signal /CAS to L level, and setting row address strobe signal /RAS and write enable signal /WE to H level. The read command instructs reading of data, and command decoder
904
accordingly supplies a reading operation instruction signal &phgr;or to control circuit
906
. Internal address generating circuit
908
takes in external address signal ADD synchronously with clock signal CLK, generates an internal column address signal from the received external address signal in response to the reading operation instruction signal from command decoder
904
, and latches the generated internal address signal under the control of control circuit
906
.
Column selecting circuit
912
performs the column selecting operation according to the column address signal from internal address generating circuit
908
, and selects an addressed column in memory cell array
900
. Data of a selected memory cell is read synchronously with clock signal CLK via read/write circuit
914
and input/output circuit
916
under the control of control circuit
906
. The period required from supply of read command RD to external output of valid data is referred to as CAS latency.
FIG. 45
illustrates waveforms in data reading with the CAS latency of 2. The number of data that are consecutively read after one read command is supplied is referred to as a burst length.
FIG. 45
illustrates a data reading operation with the burst length of 2. Accordingly, after two clock cycles from supply of read command RD, in two clock cycles #f and #g, data Q
0
and Q
1
are defined to be sampled by an external unit.
In clock cycle #h, a write command WR is supplied to designate writing of data. Write command WR is issued by setting chip select signal /CS, column address strobe signal /CAS, and write enable signal /WE all to L level, and setting row address strobe signal /RAS to H level. When write command WR is supplied, command decoder
904
activates a writing operation instruction signal &phgr;w and supplies it to control circuit
906
. In response to activation of writing operation instruction signal &phgr;w fr

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