Radiation imagery chemistry: process – composition – or product th – Registration or layout process other than color proofing
Reexamination Certificate
1999-02-16
2001-02-13
Young, Christopher G. (Department: 1756)
Radiation imagery chemistry: process, composition, or product th
Registration or layout process other than color proofing
C430S312000, C430S394000
Reexamination Certificate
active
06187486
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88100055, filed Jan. 5, 1999, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a multi-exposure process.
2. Description of the Related Art
Typically, the semiconductor process comprises four modules including the diffusion module, the etching module, the thin film module and the photo module. The photo module, in which the photolithography process is performed, is used to replicate the etching patterns for the etching module or implanting patterns for the thin film module on the photomask onto the wafer. Hence, the quality of the semiconductor device depends on whether the resolution of the photolithography process is good.
Additionally, as the size of the device becomes smaller, the tolerance of the design rule becomes smaller and it gradually approaches to the error produced by the process machine, which is called the resolution of the machine. In other words, it is getting more and more difficult to fabricate a device with a tolerance that satisfies the requirement of the design in the deep sub-micron process. Ideally, the misalignment does not occur when the pattern is replicated from the photomask onto the wafer by photolithography in the formation process of a contact or a plug. Therefore, the contact hole or the via hole lands on the location predetermined for forming the contact or the plug. However, it is difficult to align the photomask with the wafer in deep sub-micron process.
Besides the method of buying expensive machines with high resolution, the size of the pattern, such as line width, can be adjusted to increase the alignment allowance to overcome the misalignment problem. In this method, not only the cost is reduced, but also the process window becomes larger and the yield is increased.
In conventional photolithography process, the pitch of the mask is fixed, wherein the pitch is a distance composed of a line width and a space. Since the pitch of the mask is fixed, the pitch of the pattern replicated from the photomask onto the wafer is fixed. However, the exposure energy, the exposure time and the exposure depth of focus (DOF) affects the size of the line width and the space of the pattern replicated from the photomask onto the wafer.
When using the positive photoresist, the exposure region is reduces as the exposure energy or the exposure time is decreased. At the same time, the line width is increased and the space is decreased. Conversely, the line width is decreased and the space is increased when the exposure energy or the exposure time is increased. Nevertheless, the conditions of incomplete development, known as scumming, and the incomplete pattern easily occur, because the line width and the space are adjusted by changing the exposure energy or the exposure time. Hence, the resolution of the pattern replicated from the photomask onto the wafer is poor and the yield is low.
Moreover, another method for adjusting the line width and the space using the precondition of the fixed pitch comprises the steps of forming a hard mask layer to cover a target layer that is going to be patterned. Then, the hard mask layer is patterned by replicating the pattern of the photomask onto the hard mask layer. A conformal layer is formed on the patterned hard mask layer. Thereafter, an etching back process is performed to form a spacer on the sidewall of the hard mask layer. Next, the target layer is patterned by using the hard mask and the spacer as an etching mask. However, the processing sequence of this method is rather complicated and the throughput is low. Usually, the negative etching bias also can be used to shrink line width at a fixed pitch. However, the amount of the shrinkage is not significant enough.
SUMMARY OF THE INVENTION
The invention provides a multi-exposure process to improve the resolution of the replicating pattern and enhance the yield. By using the invention, the processing sequence is simplified and the throughput is increased.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a multi-exposure process. A wafer having a photoresist formed thereon is provided. A photomask aligned with the wafer is provided. A first exposure process is performed to simultaneously form a first exposure region and an unexposed region in the photoresist. A first relative and parallel shift movement is performed to make a relative and parallel shift with a first distance between the wafer and the photomask, wherein the first relative and parallel shift movement has a first direction and a first relative shift distance. A second exposure process is performed to convert a portion of the unexposed region adjacent to the first exposure region into a second exposure region in the photoresist. A second relative and parallel shift movement is performed to make a relative and parallel shift with a second distance between the wafer and the photomask, wherein the second relative and parallel shift movement has a second direction and a second relative shift distance. A third exposure process is performed to convert a portion of the remaining unexposed region adjacent to the first exposure region into a third exposure region in the photoresist. By performing the multi-exposure process, the size of the line width can be enlarged or shrunk at the precondition of the fixed pitch. Moreover, the process window is increased and the yield is enhanced. Furthermore, the throughput can be increased.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5830610 (1998-11-01), Leroux et al.
Lai Jun-Cheng
Lou Chine-Gie
Tu Yeur-Luen
Huang Jiawei
Patents J C
Worldwide Semiconductor Manufacturing Corp.
Young Christopher G.
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