Single-crystal – oriented-crystal – and epitaxy growth processes; – Forming from vapor or gaseous state – With decomposition of a precursor
Reexamination Certificate
1999-02-01
2001-12-11
Kunemund, Robert (Department: 1765)
Single-crystal, oriented-crystal, and epitaxy growth processes;
Forming from vapor or gaseous state
With decomposition of a precursor
C117S097000, C117S915000, C216S002000, C216S095000, C438S455000
Reexamination Certificate
active
06328796
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to methods for the growth of single crystal material layer on a polycrystalline substrate.
2. Description of Related Art
A large area, inexpensive substrate for the growth of epitaxial layers (especially silicon carbide, SiC) has been a long-sought goal. Currently, single crystal 6H- or 4H-polytype SiC substrates are the predominantly used substrates for epitaxial SiC growth. However, single crystal SiC substrates are very expensive and are currently available in small substrates sizes of 2 inch diameter or less.
An alternate approach that has been investigated for SiC epitaxial growth on a large area substrate has been the growth of the cubic polytype of SiC (also referred to as the 3C or beta polytype of SiC) on a silicon substrate. The 3C polytype of SiC is desirable for its high electron mobility and high breakdown field for power electronic device applications, and its isotropic mobility characteristics for sensor applications. However, the large lattice mismatch (~20%) and thermal expansion mismatch (~8%) between SiC and silicon have to date prevented the growth of high quality SiC epitaxial layers on silicon substrates. An additional problem with this approach is that the optimum growth temperature for SiC epitaxial growth is between 1500° C. and 1600° C., well above the 1350° C. maximum use and the 1450° C. melting temperature of a silicon substrate.
Another approach for 3C—SiC growth on silicon substrate has been to first carbonize the silicon surface forming a thin 3C—SiC layer, and then to grow 3C—SiC epitaxial layers on the carbonized silicon surface at a growth temperature below 1350° C. U.S. Pat. No. 4,855,254, issued to Eshita et al. describes a method to carbonize silicon substrate. There is a tendency for anti-phase domains to form in the epitaxial layer for 3C—SiC growth on a (100) orientation silicon substrate. U.S. Pat. No. 5,230,768, issued to Furukawa et al. and U.S. Pat. No. 5,279,701, issued to Shigeta, et. al. describes a method to to obtain improved growth of 3C—SiC material on a silicon substrate silicon substrate that is oriented miscut from (100) orientation. More recent studies have included the growth of 3C—SiC on silicon-on-insulator (SOI) substrates. U.S. Pat. No. 5,759,908, issued to Steckl et al. describes a method to fabricate SiC on SOI substrates.
It is sometimes possible to obtain polytype conversion in growth of SiC depending on the growth temperature, and thus hexagonal polytypes of SiC can sometimes be grown on a cubic polytype of SiC.
It is sometimes possible to obtain polytype conversion in growth of SiC depending on the growth temperature, and thus hexagonal polytypes of SiC can sometimes be grown on a cubic polytype of SiC for high temperature growth.
Wide bandgap gallium nitride (GaN) material has recently been demonstrated to be very beneficial for microwave power transistor applications, and for blue-green laser and light emitting diodes (LED). GaN epitaxial layers have typically been grown on a sapphire substrate or on single crystal SiC substrates. There are continuing searches for new substrates for GaN growth. Sapphire is electrically insulating, a disadvantage for vertical current conducting optical emitters and power devices, and has relatively high thermal impedance which is a disadvantage for high power microwave devices. The best quality GaN epitaxial layers have been obtained for material grown on SiC substrates, however, single crystal SiC substrates are very expensive and are only available in small substrate sizes. GaN epitaxial growth on silicon substrates is recently being investigated as an approach to obtain GaN epitaxial growth on large area substrates. There is however, significant thermal expansion mismatch between GaN and silicon which leads to cracking of the epitaxial layer for thick GaN epitaxial layers. There is also a significant lattice mismatch between GaN lattice and silicon lattice which limits the quality of GaN epitaxial layers grown on a silicon substrate. In addition, the silicon substrate is not suitable for microwave applications because of microwave loss in the conducting silicon substrate.
For GaN growth on a silicon substrate, different poly-types of GaN have a tendency to form, depending on the orientation of silicon substrate. Typically cubic polytypes of GaN will form on a (100) orientation silicon substrate. Likewise, hexagonal polytypes of GaN will form on a (111) orientation silicon substrate. In some cases, a preferred method to grow GaN on silicon is to first form a thin layer of cubic-SiC forms on the silicon surface by carbonization prior to the growth of GaN. There is a relatively good lattice constant match between cubic-GaN and cubic-SiC. Care should be taken in the GaN growth process, to avoid the formation of silicon nitride on the silicon surface prior to the GaN growth.
Non-single crystal ceramic substrates can be designed to have optimized mechanical, thermal expansion, thermal conduction, or electrical conduction properties for particular applications. One polycrystalline ceramic substrate that has especially desirable properties is poly-SiC. Poly-SiC substrates are manufactured commercially in hot pressed sintered form, reaction bonded form, and chemical vapor deposited (CVD) form. The CVD poly-SiC substrates are available commercially in substrate sizes up to 200 mm diameter, with thermal impedance as high as 310 W/mK, electrical resistivity as high as 100,000 ohm-cm at room temperature, electrical impedance as low as 1 ohm-cm, maximum use temperature greater than 2000° C., and excellent thermal expansion matching to single crystal cubic-SiC. Hot pressed sintered poly-SiC substrates are commercially available that have many of the above characteristics, but with electrical impedances as low as 0.1 ohm-cm. Ceramic AlN substrates are available commercially is substrate sizes to 100 mm square, with thermal impedances as high as 170 W/mK, electrical resistivity as high as 10
−13
ohm-cm at room temperature, and excellent thermal expansion matching to single crystal GaN. Polycrystalline diamond has thermal conductivity as high as 1000 W/mK. Ceramic silicon nitride has good thermal expansion matching to silicon. Ceramic graphite substrates are available with electrical impedances as small as 0.001 ohm-cm at room temperature. AlSiC substrates are commercially available, and have good expansion matching to silicon. Mechanical, thermal, optical and electrical data on a large variety of ceramic substrate materials can be found on the National Institute of Standards WWW Version of the Structureal Ceramic web site for ceramics:
http://www.ceramics.nist.gov/srd/scd/scdquery.htm
http://www.ceramics.nist.gov/srd/scd/Z00390.htm
A provisional patent application filed on Jun. 30, 1998 by Kub and Hobart discussed several techniques to make ultra-thin wafer bonded material layers.
One method of fabricating thin wafer bonded semiconductor layer involves bond-and-etch back (BESOI) technique. The BESOI technique involves bonding a wafer an etch stop layer to an oxidized silicon handle wafer, thinning the wafer that contain the etch stop layer using grinding, chemically etching to the etch stop layer, and then etching the etch stop layer. A key step in the BESOI process is the method of forming the etch stop layer. Heavily doped boron concentration (>10
20
cm
−3
) layer have been used as the etch stop layer. U.S. Pat. No. 5,540,785, issued to Dennard et al. describes a method to fabricate BESOI that uses a heavily boron doped etch stop layer that has a small percentage of germanium added to heavily boron doped etch stop layer to produce a defect free epitaxial layer. U.S. Pat. No. 5,013,681 issued to Godbey et al. describes a method to fabricate BESOI that uses a strained SiGe etch stop. U.S. Pat. No. 5,024,723 issued to Goesele et al. describes a method to fabricate BESOI by implanting carbon ion into a substrate to form an etch stop layer. The disadvantage of all the BESOI approach
Hobart Karl D.
Kub Francis J.
Karasek John J.
Kunemund Robert
Marciniszyn Jane B.
The United States of America as represented by the Secretary of
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