Process of fabricating buried diffusion junction

Details Process of fabricating buried diffusion junction Process of fabricating buried diffusion junction

1998-04-20

2001-04-24

Everhart, Caridad (Department: 2825)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

C438S439000, C438S425000

Reexamination Certificate

active

06221731

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application Serial No. 87100301, filed Jan. 12, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates in general to a process of fabricating semiconductor IC devices and, in particular, to a process of fabricating buried diffusion junction thereof. More particularly, this invention relates to a process of fabricating buried diffusion junction in combination with the shallow-trench isolation for memory device cell unit transistors.
2. Description of Related Art
Buried diffusion junctions in IC devices are generally fabricated selfaligned with the transistor source/drain regions of cell units of memory devices, thereby forming continuous interleaving regions of the buried diffusion junction and the shallow-trench isolation. The buried diffusion junction regions thus formed constitute the source/drain regions for the device transistor. Among each pair of these source/drain regions, one of them can be utilized to connect directly to the bitline for the transistor-based cell unit.
MOS transistors in semiconductor IC memory devices can be considered as a four-terminal device including a gate and a pair of source/drain terminals. In a complete semiconductor memory IC device, consecutive MOS transistors must be isolated from each other utilizing electrical isolation structures to avoid mutual electrical short-circuiting. In general, a technique of local oxidation of silicon (LOCOS) is frequently employed to form device isolation regions underneath the surface of the device substrate by forming a thick layer of oxide. As the technique of LOCOS matures, low-cost, effective and reliable device isolation structures are thus possible.
However, there are still some disadvantages with LOCOS. Among the most obvious, problems in relation to the accumulation of mechanical stresses as well as the formation of bird's beak surrounding the isolation regions are the most noticeable. The problem caused by the formation of bird's beak, in particular, renders the reduced effectiveness of LOCOS isolation regions in small-sized devices. In order to solve this problem, conventional practices have employed the use of shallow-trench isolation structures for small devices. The advantage of larger thickness of shallow-trench isolation structures not only assists in improved isolation, but it also provides rigid and planar surface for the isolation structure.
Conventionally, bitlines leading to the memory cell units are electrically connected to the corresponding source/drain regions of the transistors by metallization via contact holes formed in the insulation layer. However, as the technology of device integration advances, device dimensions are reduced. Refined fabrication resolution thus brings increased difficulties in implementing the necessary alignment for the contact holes with respect to their corresponding transistor source/drain regions. Buried bitlines thus provides as a form of more reliable and easier-to-implement electrical connection to the cell unit transistors. Moreover, buried bitlines occupy no additional device surface area which is a fact advantageous in improving device integration densities.
However, conventional arrangement for buried diffusion junction and shallow-trench isolation can not allow them to be present on the same layout. If the fabrication procedure for buried diffusion junction is combined with that for the shallow-trench isolation, the buried diffusion junctions will be cut in parts by the presence of shallow-trench isolation regions. This constrains the employment of buried diffusion junctions in devices installing shallow-trench isolations. Meanwhile, conventional buried bitlines are fabricated after the formation of the main structure of the transistors which is a practice that adds to the complexity of the entire device fabrication procedure.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a process for fabricating buried diffusion junction that can be combined with the shallow-trench isolation for the memory device cell unit transistor wherein both the junction and the isolation can be formed in the same layout.
It is another object of the present invention to provide a process for fabricating buried diffusion junction in combination with shallow-trench isolation for the memory device cell unit transistor wherein the junction is free from being inadvertently cut apart to cause open-circuiting.
The present invention achieves the above-identified objects by providing a process for fabricating a buried diffusion junction for a semiconductor integrated circuit device. The process includes the step of forming a first oxide layer over the surface of the device substrate, followed by the formation of a patterned silicon nitride layer, and the silicon nitride layer reveals the surface of the first oxide layer. An ion implantation region is then formed in the device substrate in the region underneath the revealed first oxide layer. The first oxide layer is then further oxidized again to form a second oxide layer and also turns the ion implantation region underneath the second oxide layer into a buried diffusion junction. The silicon nitride layer is then patterned covering the device active region, thereby exposing portions of the first oxide layer. A shallow-trench isolation region is then formed in the device substrate by performing an etching procedure utilizing the second oxide layer and the silicon nitride layer as shielding mask.


REFERENCES:
patent: 5677232 (1997-10-01), Kim et al.
patent: 5858842 (1999-01-01), Park
patent: 5911110 (1999-06-01), Yu
patent: 6020251 (2000-02-01), Peng et al.

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