Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1998-10-30
2001-05-22
Gulakowski, Randy (Department: 1746)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S906000, C438S963000, C216S067000
Reexamination Certificate
active
06235644
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method of fabricating multilevel interconnects of a semiconductor device, and more particularly to a method of improving the etching process of metallization.
2. Description of the Related Art
In many semiconductor circuits with a high integration, a plug is formed as a multilevel interconnect in an integrated circuit, or an interconnect between devices. In a conventional process, after forming an inter-metal dielectric layer on a first wiring layer, a via hole is formed to penetrate through the inter-metal dielectric layer and the first wiring layer is exposed. A metal layer is formed on the inter-metal dielectric layer and fills the via. The metal layer is then etched back to form a plug for interconnection.
Due to the high melting point, the high thermal expansion coefficient equivalent to silicon, a moderate internal stress, and a very good step coverage by chemical vapour deposition, tungsten is a very common material used to form a plug. A process with etch back is commonly adapted to form a tungsten plug for multilevel interconnection in the industry.
A conventional etch back process of fabricating a tungsten plug includes two steps. The first one is a main etch step, the second one is an over etch step. The main etch is performed by dry etch after the deposition of the metal layer. The unwanted metal layer on the surface of the inter-metal dielectric layer is removed by main etch. Over etch is performed to remove the residue metal layer after the main etch to ensure that the unwanted metal layer is removed completely. A conventional method of forming a tungsten plug with etch back is introduced with the reference of
FIG. 1A
to
FIG. 1E
as follows.
Referring to
FIG. 1A
, a dielectric layer
102
is formed on a substrate
100
which comprises a metal oxide semiconductor (MOS) device and a first metal layer. Referring to
FIG. 1B
, by covering a photo-resist layer on the dielectric layer
102
, using photolithography and etching, a via hole or a contact window
104
for connecting different metal layers is defined, and the first metal layer is exposed. Referring,
FIG. 1C
, a thin metal glue layer
106
, such as a titanium layer, is formed on the exposed first metal layer and the dielectric layer
102
. Using physical vapour deposition, a barrier layer
108
, such as a titanium nitride layer, having a thickness of 800 Å to 1200 Å is formed on the metal glue layer
106
. A refractory and good conductive second metal layer
100
, for example, a tungsten layer is formed on the barrier layer
108
and fills the via hole
104
. Referring to
FIG. 1D
, using the barrier layer
108
as an etch stop, the second metal layer
110
is etched back to form a metal plug
110
a.
Referring to
FIG. 2
, the etch back process normally includes two steps, a step of main etch
200
and a second step of over etch
202
.
After the formation of the second metal layer, using a mixture of gases containing fluorine, for example, carbon fluoride and oxygen (CF
4
/O
2
), nitrogen triofluoride and oxygen (NF
3
/O
2
), or sulfur fluoride and oxygen (SF
6
/O
2
) as a reacting gas source, main etch, such as dry etch, is performed with the barrier layer
108
as an etch stop. The second metal layer
110
is etched back, and most of the second metal layer
110
on the dielectric layer
102
is removed to form a metal plug. Over etch is then performed to remove the metal residue on the dielectric layer
102
. The metal layer to be etched is thus removed completely.
Referring to
FIG. 1E
, with the gas source during dry etch, both etch reaction and polymerised reaction occur. Etch reaction is a reaction between metal and the plasma particles produced by the gas source. The production of the etch reaction is a volatile gas. Thus, after dry etch, the metal layer is transformed into a volatile gas and vaporised from the surface. The particles produced by the gas source are reacted with each other and polymerised into polymer
114
. The polymer
114
is then deposited over the substrate
100
. The main reaction is the etch reaction during dry etch. Therefore, after dry etch, most of the second metal layer
110
on the dielectric layer
102
is removed, but some metal residue is left and covered by the polymer
114
. An over etch is then performed to remove the metal residue for about 20 seconds to 30 seconds. However, since the residue metal is covered by the polymer
114
, a very long time, for example, 20 seconds to 1 minute, or more than 1 minute, is consumed for over etch. Consequently, the barrier layer
108
, the metal glue layer
106
, and the tungsten plug are damaged by the very time consuming over etch process. The metal plug loss caused during over etch process may cause an open contact while connecting other metal layer.
For a structure having an uneven surface, a stringer is formed due to the ragged topography during main etch. For example, referring to
FIG. 3
, on a substrate
300
having a bird's beak structure
301
, a stringer or a residue
304
is formed. Similarly, the stringer
304
is difficult to remove completely, even by over etch.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a method of improving etch back process for metal. The metal to be etch, and the polymer produced during etch process are completely removed without consuming a very long time for over etch.
To achieve these objects and advantages, and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention is directed towards a method of improving an etch back process. A substrate having a metal layer formed thereon is provided. Main etch is performed over the metal layer to form an interconnect. First over is performed over a metal residue left after the main etch. Gas flush and second over etch are performed. The gas flush is performed by a consistent flow method, or a pump-purge method.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
REFERENCES:
patent: 5174856 (1992-12-01), Hwang et al.
patent: 5188980 (1993-02-01), Lai
patent: 5227337 (1993-07-01), Kadomura
patent: 5854137 (1998-12-01), Kuo
patent: 5915202 (1999-06-01), Lo et al.
patent: 5990018 (1999-11-01), Ho et al.
patent: 6051505 (2000-04-01), Chu et al.
Ahmed Shamim
Gulakowski Randy
United Microelectronics Corp.
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