Drive circuit for liquid crystal display apparatus

Details Drive circuit for liquid crystal display apparatus Drive circuit for liquid crystal display apparatus

1998-10-13

2001-10-16

Hjerpe, Richard (Department: 2674)

Computer graphics processing and selective visual display system

Plural physical display element control system

Display elements arranged in matrix

C345S090000

Reexamination Certificate

active

06304240

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a drive circuit for a liquid crystal display apparatus, and more specifically, to a dot inversion drive circuit.
Typical drive methods employed for driving liquid crystal apparatuses include frame inversion, line inversion and dot inversion, and among these, line inversion and dot inversion in particular, are drive methods suited for effecting cancellation of cross talk. However, since dot inversion requires complex control signals, a line inversion drive method that offers more advantages overall is the mainstream method at present.
Since the dot inversion drive method is similar to the line inversion drive method, it is possible to adopt in the line inversion drive circuit a structure that is normally used in the line inversion drive method to implement dot inversion drive. Consequently, the main focus in the development of drive circuits for liquid crystal display apparatuses has been placed on line inversion drive circuits due to such factors as development cost and the product quality control, and such line inversion drive circuits have often been employed in the dot inversion drive method.
A line inversion drive circuit
101
is illustrated in FIG.
13
. The line inversion drive circuit
101
includes driver cells
103
-
1
to
103
-n, the number of which corresponds to the number of pixels in the liquid crystal display apparatus. The driver cells
103
-
1
to
103
-n have a function for outputting output voltages OUT-
1
to OUT-n in correspondence to input data DT-
1
to DT-n respectively. It is to be noted that since driver cells
103
-
1
to
103
-n are structured almost identically to one another, the driver cell
103
-
1
will be explained below as a typical example.
The driver cell
103
-
1
includes a gradient voltage selection circuit (hereafter referred to as a “decoder”)
105
and an amplifier circuit (hereafter referred to as an “amplifier”)
107
. The decoder
105
selects one of input gradient voltages V
1
to Vn based upon the data DT-
1
during every raster cycle to output it as a decoder output Decout. It is to be noted that the explanation is given here on a case in which there are 64 gradations, i.e., the gradient voltage Vn=V
64
.
Next, the structure of the decoder
105
is explained. The decoder
105
comprises an area
111
including N channel transistors (hereafter referred to as an “N channel decoder area”) and an area
113
includes P channel transistors (hereafter referred to as a “P channel decoder area”).
FIG. 14
illustrates details of the N channel decoder area
111
and the P channel decoder area
113
.
In the N channel decoder area
111
, a plurality of enhancement type N channel transistors and a plurality of depletion type N channel transistors are provided in a matrix. In addition, in the direction of the rows in the figure, the drains and the sources of transistors that are adjacent in the horizontal direction are connected to each other, whereas in the direction of the columns, the gates of transistors that are adjacent in the vertical direction are connected to each other. Likewise, in the P channel decoder area
113
, a plurality of enhancement type P channel transistors and a plurality of depletion type P channel transistors are provided in a matrix. In the direction of the rows, the drains and the sources of transistors that are adjacent in the horizontal direction are connected to each other, whereas in the direction of columns, the gates of transistors that are adjacent in the vertical direction are connected to each other.
The individual rows of the plurality of transistors provided in a matrix in both the N channel decoder area
111
and the P channel decoder area
113
correspond to the gradient voltages V
1
to V
64
respectively, whereas the individual columns correspond to the individual bits (complementary) D
0
, /D
0
to D
7
, /D
7
in the data DT-
1
. It is to be noted that the gradient voltage Vm in
FIG. 14
indicates an arbitrary gradient voltage among the gradient voltages V
1
to V
64
.
In addition, the enhancement type N channel transistors and the depletion type N channel transistors in the N channel decoder area
111
are provided so that one of the gradient voltages V
1
to V
64
is output as the decoder output Decout in conformance to the level of the value of the data DT-
1
. Likewise, the enhancement type P channel transistors and the depletion type P channel transistors in the P channel decoder area
113
are provided so that one of the gradient voltages V
1
to V
64
is output as the decoder output Decout in conformance to the level of the value of the data DT-
1
.
The driver cell
103
-
1
structured as described above outputs one of the gradient voltages V
1
to V
64
that corresponds to the data codes
00
to FF (HEX) of the data DT-
1
respectively, as an output voltage OUT-
1
as illustrated in FIG.
15
.
Depending upon the type of liquid crystal display apparatus in use, it may be necessary to reverse the relationship between the data DT-
1
and the output voltage OUT-
1
in the driver cell
103
-
1
. Namely, there is a case in which the gradient voltage V
64
must be selected in correspondence to the data code
00
and the gradient voltage V
1
must be selected in correspondence to the data code FF (indicated by the solid line in
FIG. 15
) and there is also a case in which the gradient voltage V
1
must be selected in correspondence to the data code
00
and the gradient voltage V
64
must be selected in correspondence to the data code FF (indicated by the dotted line in FIG.
15
).
In addition, when the data DT-
1
of the line inversion drive circuit
101
conforms to, for instance, the 5V specifications and the arbitrary gradient voltage Vm at the driver cell
103
-
1
is at 0V, the gradient voltage Vm can be output as the decoder output Decout only in the N channel decoder area
111
. However, when the gradient voltage Vm is at 5V, for instance, the N channel transistors constituting the N channel decoder area
111
will not be turned on, and consequently, it will not be possible to output the gradient voltage Vm as the decoder output Decout. For this reason, in the line inversion drive method in which it is necessary to reverse the relationship between the data codes
00
to FF and the gradient voltages V
1
to V
64
depending upon the type of liquid crystal display apparatus, the driver cells
103
-
1
to
103
-n always assume a structure in which both the N channel decoder area
111
and the P channel decoder area
113
are provided as illustrated in
FIGS. 13 and 14
.
A dot inversion drive circuit in the prior art adopts the structure of the line inversion drive circuit
101
as explained earlier. The dot inversion drive circuit in the prior art is now described in reference to
FIGS. 16 and 17
.
The dot inversion drive circuit in the prior art adopts a structure provided with driver cells
121
, the number of which corresponds to the number of pixels in the liquid crystal display apparatus, and the driver cells
121
are each provided with a decoder
123
illustrated in FIG.
16
. The decoder
123
includes two N channel decoder areas
131
and
133
and two P channel decoder areas
135
and
137
. Gradient voltages V
1
to V
64
are input to the N channel decoder area
131
and the P channel decoder area
135
, whereas gradient voltages V
65
to V
128
are input to the N channel decoder area
133
and the N channel decoder area
137
.
In a driver cell
121
in the dot inversion drive circuit, two gradient voltages are allocated in correspondence to a single set of data, unlike in the driver cell
103
-
1
in the line inversion drive circuit
101
described earlier. For instance, the gradient voltage V
1
and the gradient voltage V
128
are selected with the data code
00
of data DT as indicated by the solid line in
FIG. 17
, whereas the gradient voltage V
64
and the gradient voltage V
65
are selected with the data code FF.
As in the case of the line inversion drive circuit
101
described above, in the driver cell
12

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