Semiconductor device manufacturing: process – Making device or circuit emissive of nonelectrical signal
Utility Patent
1998-01-23
2001-01-02
Mulpuri, Savitri (Department: 2812)
Semiconductor device manufacturing: process
Making device or circuit emissive of nonelectrical signal
C438S039000, C438S046000, C438S462000
Utility Patent
active
06168962
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to a method of manufacturing a semiconductor light emitting device having semiconductor layers, including p-type and n-type layers, formed on a substrate to have a p-side electrode and an n-side electrode on the main surface side of the substrate. More particularly, this invention relates to a method of manufacturing a semiconductor light emitting device adapted to improve the chip yield, i.e. the number of semiconductor light emitting chips available upon breaking a wafer from the backside thereof into chips, such as in wafer breakage for bluish-light semiconductor light emitting devices having gallium-nitride based compound semiconductor layers formed on a sapphire substrate.
The conventional semiconductor light emitting device for emitting bluish light has a chip (hereinafter referred to as “LED chip”) structure, for example, as shown in FIG.
4
. That is, the LED chip includes a sapphire substrate
21
on which an n-type layer (cladding layer)
23
is formed by epitaxially growing an n-type GaN, for example. On the n-type layer
23
, an active layer (light emitting layer)
24
, e.g. of InGaN-based compound semiconductor having a bandgap energy lower than that of the cladding layer to define an emission light wavelength, wherein the “InGaN-based” means a chemical composition having In and Ga in a ratio to be varied. On the active layer
24
, a p-type layer (cladding layer)
25
is formed, for example, of p-type GaN. The semiconductor layers has a p-side (upper) electrode
28
on a surface thereof and an n-side (lower) electrode
29
on a surface of the n-type layer
23
exposed by partly etching the semiconductor overlying layers. Incidentally, the n-type layer
23
and the p-type layer
25
, in many cases, have respective AlGaN-based compound semiconductor layers on the active layer sides in order to improve carrier confining effects, wherein the “AlGaN-based” means a chemical composition having Al and Ga in a ratio to be varied.
For forming the LED chips, semiconductor layers are first formed on a surface of a sapphire substrate wafer. Then, the semiconductor layers thus formed are partly removed away by etching into a pattern that the type layer
23
is exposed at electrode forming areas as well as chip peripheral areas and the p-type layer is left at areas other than these areas. After forming electrodes
28
,
29
, the wafer is subjected to slicing from the backside thereof so as to be broken along cutting lines S, as shown in the figure, into separate chips. In this manner, the etch pattern for exposing the n-type layer
23
is in a form that the p-type layer
25
is removed at chip peripheral areas as shown in
FIG. 5
so that the wafer is broken there into individual chips. This is because of the following reasons. That is, since the wafer of this kind is difficult to cleave, the semiconductor layers are reduced in thickness at areas where braking is performed. Moreover, if an unetched area is left at an end area of the n-type layer
23
for providing the n-type electrode
29
and if the position of breaking deviates from the normal position, the conductor wire thereafter bonded possibly leads to electric shorting. This should be avoided. In addition, cracks tend to occur in the active layer, as the situation of wafer breaking may be.
However, if the semiconductor layers are etched at chip peripheral areas to expose the n-type layer as stated above, the etch width B has to be determined to approximately 30 &mgr;m as taking into consideration deviation in slicing for carrying out wafer breaking. In such a case, if the resulting chip is in a square form having a side dimension A of approximately 360 &mgr;m, then the percentage of the area defined by the width B provided, for each chip, between the chips with respect to the effective chip area accounts for ({A×B+(A+B)×B}/A×A) accounts for as high as approximately 17%. To this end, if the etch areas are provided for wafer breaking around the chips, the chip yield from the wafer is greatly reduced, thus raising a problem of mounting up of cost.
SUMMARY OF THE INVENTION
It is a primary object of the present invention to improve chip yield by eliminating the useless space in the semiconductor layer formed on a wafer that is removed away by etching to divide the wafer into chips, thereby reducing manufacture cost.
It is another object of the present invention to provide a method of manufacturing a semiconductor light emitting device wherein improvement is made for the chip pattern so that, even if the breaking position deviates, there is almost no fear of remaining a p-type layer left unetched at end areas of an n-type layer exposed for providing an n-side electrode.
In accordance with the present invention, there is provided a method of manufacturing a semiconductor light emitting device comprising the steps of:
forming semiconductor overlying layers on a substrate in a state of a wafer for providing a plurality of chips, the semiconductor overlying layers including first and second conductivity type layers;
removing part of the semiconductor overlying layers including the first conductivity type layer on a surface thereof so as to expose part of the second conductivity type layer;
forming, for each chip, electrodes respectively in connection with the surface of the first conductivity type layer and the surface of the exposed second conductivity type layer;
dividing the wafer into individual chips; and
wherein the exposed areas of the second conductivity type semiconductor layer is provided only part of a peripheral area of the chip so that the first conductivity type semiconductor layer is directly separated during dividing the wafer into individual chips.
Here, the term “division (or dividing)” means separation of a wafer into chips involving by breaking, cleaving, dicing, and so forth.
This eliminates the necessity of providing the space for etch-removing, for dividing the wafer into chips, part of the semiconductor overlying layers at around the chip, thereby increasing the number of chips available from one wafer.
The chip may be rectangular in plan form, the exposed area of the second conductivity type semiconductor layer be formed at one corner area of the rectangular chip so that four adjacent rectangular chips have the exposed areas thereof formed continuous at bordering corners of the four adjacent chips. With such a method, even if the position of breaking deviates, there is no possibility that unetched area of the p-type layer is left at an end area of the exposed n-type layer, and no problem arises during wire bonding.
The substrate may be a sapphire substrate, and the semiconductor overlying layers being of a gallium-nitride based compound semiconductor, wherein slicing is performed from a surface side of the semiconductor overlying layers and thereafter slicing is made from a back side of the substrate to thereby carry out breaking. With such a method, breaking is further facilitated.
Here, the “gallium-nitride based compound semiconductor” refers to a semiconductor of a compound of Ga as a group-III element and N as a group-V element, wherein part the group-III element Ga may be substituted for other group-III elements such as Al and In and/or part the group-V element N may be substituted for other group-V elements such as P and As. Meanwhile, “slicing” means to form, by using a diamond pen or the like, a line or groove for performing breaking.
The above described objects and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5418190 (1995-05-01), Cholewa et al.
patent: 5814532 (1998-09-01), Ichihara
patent: 5814533 (1998-09-01), Shakuda
patent: 5858808 (1999-01-01), Igel et al.
patent: 5904548 (1999-05-01), Orcutt
patent: 5939735 (1999-08-01), Tsutui et al.
Itoh Norikazu
Nakata Shunji
Shakuda Yukio
Sonobe Masayuki
Tsutsui Tsuyoshi
Arent Fox Kintner Plotkin & Kahn
Mulpuri Savitri
Rohm & Co., Ltd.
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