Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Coating selected area
Utility Patent
1999-02-04
2001-01-02
Gorgos, Kathryn (Department: 1744)
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Coating selected area
C205S125000, C205S182000
Utility Patent
active
06168704
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor fabrication technology and, more particularly, to electrochemical deposition processes for filling contact openings and vias and creating interconnect lines with metal.
2. Description of the Related Art
The ideal interconnect conductor for semiconductor circuitry will be inexpensive, easily patterned, have low resistivity, and high resistance to corrosion, electromigration, and stress migration. Aluminum is most often used for interconnects in contemporary semiconductor fabrication processes primarily because it is inexpensive and easier to etch than, for example, copper. However, because aluminum has poor electromigration characteristics and high susceptibility to stress migration, it is typically necessary to alloy aluminum with other metals.
As semiconductor device geometries shrink and clock speeds increase, it becomes increasingly desirable to reduce the resistance of the circuit metallization. The one criterion that is most seriously compromised by the use of aluminum for interconnects is that of conductivity. This is because the three metals with lower resistivities (aluminum has a resistivity of 2.824×10
−6
ohms-cm at 20° C.), namely, silver with a resistivity of 1.59×10
−6
ohms-cm (at 20° C.), copper with a resistivity of 1.73×10
−6
ohms-cm (at 20° C.), and gold with a resistivity of 2.44×10
−6
ohms-cm (at 20° C.), fall short in other important criteria. Silver, for example, is relatively expensive and corrodes easily, and gold is very costly and difficult to etch. Copper, with a resistivity nearly on par with silver, immunity from electromigration, high ductility (which provides high immunity to mechanical stresses generated by differential expansion rates of dissimilar materials in a semiconductor chip) and high melting point (1083° C. vs. 659° C. for aluminum), fills most criteria admirably. However, copper is exceedingly difficult to etch in a semiconductor environment. As a result of the difficulty in etching copper, an alternative approach to forming vias and metal lines must be used. The damascene approach, consisting of etching openings such as trenches in the dielectric for lines and vias and creating in-laid metal patterns, is the leading contender for fabrication of sub-0.25 micron (sub-0.25 &mgr;) design rule copper-metallized circuits.
In a typical single-damascene copper process flow, as shown in FIGS.
1
A-
1
E, a first dielectric layer
100
is deposited on a second dielectric layer
105
on a wafer
107
. The second dielectric layer
105
has an intermetal via connection
110
disposed therein. If necessary, the first dielectric layer
100
is planarized using chemical-mechanical planarization (CMP). A metallization pattern is then formed by using a patterned photomask
115
(
FIG. 1A
) and photolithography. For example, openings (such as trench
120
) for conductive metal lines, contact holes, via holes, and the like, are etched into the first dielectric layer
100
(FIG.
1
B). The patterned photomask
115
is then stripped and a thin barrier metal layer of tantalum
125
A and a copper seed layer
125
B are then applied to the entire surface using vapor-phase deposition (FIG.
1
C). The barrier metal layer of tantalum
125
A and the copper seed layer
125
B blanket-deposit the entire upper surface
130
of the first dielectric layer
100
as well as the side and bottom surfaces of the trench
120
, forming a conductive surface
135
, as shown in FIG.
1
C.
The bulk of the copper trench-fill is frequently done using an electroplating technique, where the conductive surface
135
is mechanically clamped to an electrode to establish an electrical contact, and the wafer
107
is then immersed in an electrolyte solution containing copper ions. An electrical current is then passed through the wafer-electrolyte system to cause reduction and deposition of copper on the conductive surface
135
. In addition, an alternating-current bias of the wafer-electrolyte system has been considered as a method of self-planarizing the deposited copper film, similar to the deposit-etch cycling used in high-density plasma (HDP) tetraethyl orthosilicate (TEOS) dielectric depositions.
This process typically produces a conformal coating
140
of constant thickness across the entire conductive surface
135
, as shown in FIG.
1
D. Once a sufficiently thick layer of copper
140
has been deposited, the surface of the wafer is planarized using CMP techniques. Ideally, this clears all copper and tantalum barrier metal from the entire upper surface
130
of the first dielectric layer
100
, leaving copper only in the copper-filled trenches (such as copper-filled trench
145
), as shown in FIG.
1
E.
In a typical dual-damascene copper process flow, as shown in FIGS.
2
A-
2
E, a first dielectric layer
200
is deposited on a second dielectric layer
205
on a wafer
207
. The second dielectric layer
205
has a “hard mask” (typically silicon nitride, SiN)
210
deposited and patterned thereon, between the first dielectric layer
200
and the second dielectric layer
205
. If necessary, the first dielectric layer
200
is planarized using CMP. Metallization patterns are then applied using the hard mask
210
and a patterned photomask
215
(
FIG. 2A
) and photolithography. Openings (such as trenches
220
and
225
) for conductive metal lines, contact holes, via holes, and the like, are etched into both the first dielectric layer
200
and the second dielectric layer
205
. The patterned photomask
215
is then stripped (
FIG. 2B
) and a thin barrier metal layer of tantalum
230
A and a copper seed layer
230
B are then applied to the entire surface using vapor-phase deposition. The barrier metal layer of tantalum
230
A and the copper seed layer
230
B blanket-deposit the entire upper surface
235
of the first dielectric layer
200
as well as the side and bottom surfaces of the trenches
220
and
225
, forming a conductive surface
240
, as shown in FIG.
2
C.
The bulk of the copper trench-fill is again done using an electroplating technique, where the conductive surface
240
is mechanically clamped to an electrode to establish an electrical contact, and the wafer
207
is then immersed in an electrolyte solution containing copper ions. An electrical current is then passed through the wafer-electrolyte system to cause reduction and deposition of copper on the conductive surface
240
.
This process typically produces a conformal coating
245
of constant thickness across the entire conductive surface
240
, as shown in FIG.
2
D. Once a sufficiently thick layer of copper
245
has been deposited, the surface of the wafer is planarized using CMP techniques. Ideally, this clears all copper and tantalum barrier metal from the entire upper surface
235
of the first dielectric layer
200
, leaving copper only in the copper-filled trenches (such as copper-filled trenches
250
and
255
), as shown in FIG.
2
E.
The dual-damascene copper process flow, as shown in FIGS.
2
A-
2
E, combines the intermetal via connection formation with the copper trench-fill deposition by etching a more complex pattern before the barrier metal layer and copper seed layer depositions and before the copper trench-fill. The trench etching continues until the via hole (such as trench
225
in
FIG. 2B
) has been etched out. The rest of the dual-damascene copper process flow, as shown in FIGS.
2
C-
2
E, is essentially identical with the corresponding single-damascene copper process flow, as shown in FIG.
1
C-
1
E. Overall, however, the dual-damascene copper process flow significantly reduces the number of processing steps and is typically a preferred method of achieving copper metallization.
Nevertheless, both the dual-damascene copper process flow, as shown in FIGS.
2
A-
2
E, and the single-damascene copper process flow, as shown in FIGS.
1
A-
1
E, entail electroplating a copper layer across the entire conductive surface. This increases the cost of t
Brown Thomas M.
Hymes Stephen W.
Advanced Micro Device Inc.
Gorgos Kathryn
Smith-Hicks Erica
Williams Morgan & Amerson
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