Radiant energy – Photocells; circuits and apparatus – Photocell controlled circuit
Reexamination Certificate
1999-01-25
2001-01-30
Le, Que T. (Department: 2878)
Radiant energy
Photocells; circuits and apparatus
Photocell controlled circuit
C250S2140RC, C348S297000
Reexamination Certificate
active
06180935
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to charge coupled device (CCD) imagers, and more particularly, to a method and means for extending the dynamic range of such imagers, to enable signal detection at illumination input conditions significantly greater than those at which CCD signal saturation is reached with conventional operating conditions, whereby signal information above the saturation level that would otherwise be lost is made available.
2. Prior Art
The need for extending the dynamic range of CCD imagers while avoiding the loss of low light signal response has resulted in the development of various methods that create a non-linear response in such devices, such as typified by that described in U.S. Pat. No. RE. 34,802 issued Nov. 29, 1994 to Michel Sayag. Essentially, the dynamic range of the pixels on a CCD sensing surface, which surface contains a plurality of pixels consisting of gate controlled charge integration wells, is limited by the charge handling capacity of the signal charge integration well sites. In the case when high intensity illumination is incident upon the CCD surface, the wells can saturate before the end of charge integration thus causing a large loss in signal response for high intensity scene information. Thus, such CCD sensing surfaces may not function satisfactorily when sensing scenes with very large in-scene variations in illumination level.
3. Problem to be Solved
Accordingly, a problem is presented by charge saturation and loss in signal response in such CCD environments, that limits the dynamic range of these imaging devices.
4. Objects
It is therefore an object of the present invention to provide a method and means for overcoming the integration well site charge saturation problem in CCD imagers.
It is another object of the invention to provide a structure and and an operating method that extends the dynamic range of CCD imagers to overcome the charge saturation problem in such imagers.
SUMMARY OF THE INVENTION
The present invention is directed to achieving dynamic range extension (DRE) in CCD imagers by varying the potential V
G
of the gate electrodes, i.e., “gates”, that are used to form pixel signal charge wells during charge integration. To this end, the CCD surface comprising the image format area is provided with a charge overflow structure, in the form of an overflow drain, i.e., a vertical overflow drain (VOD) or lateral overflow drain (LOD), that functions a) to control the signal charge spreading due to illumination overload and/or b) as a means for the control of signal integration time, commonly known as electronic shuttering. The overflow drain structure, preferably a VOD, is embodied in the image area of a typical charge coupled device (CCD), such as a frame transfer CCD, and is formed within an n-Si substrate by depositing a p− well portion therein, which in turn has two p+ regions deposited on opposite sides of an n− region deposited at the upper surface of the well. A gate electrode is formed on a dielectric layer above the p+ and n− regions on the upper surface and has a potential V
G
imposed thereon. In accordance with the invention, two different V
G
levels are applied to the gates, one long in time duration followed by one short in time duration, in a manner that provides significant extensions in dynamic range. Specifically, the lower of the two levels V
G
-LOW is applied for the long duration and the higher level V
G
-HIGH is applied for the shorter duration to the gates over the integration well sites. During the imposition of V
G
-LOW, the well sites are smaller in charge handling capacity than for the V
G
-HIGH condition. For a typical case, the level of voltage V
G
-LOW is set to achieve a maximum pixel well capacity equal to 25% to 50% of the full 100% well capacity achievable with voltage V
G
-HIGH. Also the time duration for V
G
-LOW is ideally a large fraction of the total integration time, typically greater than 90%.
With this structural arrangement and voltage pattern, upon the incidence of very intense illumination on the CCD surface during the period with voltage V
G
-LOW on the gates, pixel signal charge will typically exceed the CCD well capacity and the pixel wells will saturate before the end of charge integration, resulting in the vertical overflow drain (VOD) operating to dump excess charge to the substrate. Thus, image signal modulation at or near the high intensity region can be severely attenuated or lost completely. However, with the subsequent imposition of V
G
-HIGH for a short time period near the end of the integration interval, in keeping with the invention, signals corresponding to high intensity are not lost, since they are integrated during the short time when V
G
is set high. At the same time, all low level signals, i.e., below the 30% V
G
-LOW level, are integrated without saturation during the V
G
low state which is held for nearly the full integration time period. Accordingly, shifting V
G
to V
G
-HIGH for a short time period near the end of the integration interval (a) increases pixel charge storage capacity and (b) shortens the exposure time, which combination allows high intensity signal information to be integrated without loss by saturation.
Preferably V
G
-LOW is set above the reference signal level used in CCD imager or camera systems for automatic light control (typically ¼ to ½ full well saturation), since, if V
G
-LOW is set too low, low level signals will saturate, causing a loss in low light scene information. If set too high, high intensity signals will saturate, causing a loss in high intensity light scene information. Also, when the invention is used in CCD camera systems with exposure control gating, the DRE waveforms should adapt to changes in the varying duration of integration time.
REFERENCES:
patent: Re. 34802 (1994-11-01), Sayag
patent: 6040570 (2000-03-01), Levine et al.
“Solid State Imaging with Charge Coupled Devices”, by A. Theuwissen, pp. 176-189, published by Kluwer Academic Publishers, 1995. (Month Unknown).
Le Que T.
Lockheed Martin Corporation
Perman & Green LLP
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