Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-02-03
2001-10-09
Ho, Hoai V. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185200, C365S185210, C365S185220
Reexamination Certificate
active
06301154
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device incorporating transistors of a floating gate type adapted so as to hold data such as redundancy-replacement-use addresses and initial states of the device.
BACKGROUND OF THE INVENTION
Recently, in memory devices of large capacity, replacement of defective memory cells by redundancy circuits is executed for eliminating errors caused by defects of memory cells. A redundancy circuit of this kind is composed of spare memory cells for substituting for defective memory cells if any, and a circuit for storing addresses of the defective memory cells (hereinafter referred to as defect address) and conducting the switching from the defective memory cells to the spare memory cells. Methods roughly classified into the following two kinds are applicable as a method of storing defect addresses, depending on a type of the device used.
First of all, for volatile memories such as DRAM and SRAM, a plurality of fuses formed with polysilicon, metal, etc. are provided in a device, and the storage of defect addresses is carried out by electrically breaking the fuses, or breaking the same by a laser beam or the like.
Conventionally, since memory cells are nonvolatile per se in EPROMS, flash memories, and the like, the memory cells are, instead of fuses, adopted as memory elements so as to store defect addresses to be redundancy-saved and initial states of the device.
FIG. 5
is a circuit diagram showing a memory circuit for storing defect addresses to be redundancy-saved, or a memory circuit for storing initial states of the device, used in a conventional EPROM or flash memory. Such a memory circuit is hereinafter referred to as an option circuit. Such an option circuit is disclosed by the U.S. Pat. No. 5,267,213 (Issue Date: Nov. 30, 1993), for example.
An option circuit
1
a
is designed so as to store one bit of, for example, a defect address, composed of two floating-gate-type transistors (hereinafter referred to as floating gate transistors)
2
and
3
, N-type transistors
4
,
5
,
6
, and
7
, and P-type transistors
8
and
9
. Generally, such a memory circuit is called as CAM (content addressable memory) cell. A bias voltage V gate that is an output of a bias voltage generating circuit
10
is supplied to each gate of the floating gate transistors
2
and
3
in the option circuit
1
a
thus designed. To each gate of the N-type transistors
4
and
5
, an output of a bias voltage generating circuit
11
is commonly supplied.
These P-type transistor
8
, N-type transistor
4
, and floating gate transistor
2
are connected in series in this order between a power source voltage Vcc level and a power source voltage Vss level (ground level), while likewise these P-type transistor
9
, N-type transistor
5
, and floating gate transistor
3
are connected in series in this order between the power source voltage Vcc level and the power source voltage Vss level.
A gate of the P-type transistor
8
is connected with a node N
4
that connects the P-type transistor
9
and the N-type transistor
5
with each other, while a gate of the P-type transistor
9
is connected with a node N
3
that connects the P-type transistor
8
and the N-type transistor
4
with each other. Further, a program voltage VPRG (about 10-12V) is supplied to each drain of the N-type transistors
6
and
7
, while program signals PRG
1
and PRG
2
are supplied to gates of the N-type transistors
6
and
7
, respectively.
A source of the N-type transistor
6
is connected with a node N
1
that connects the floating gate transistor
2
and the N-type transistor
4
with each other, while a source of the N-type transistor
7
is connected with a node N
2
that connects the floating gate transistor
3
and the N-type transistor
5
with each other.
The option circuit
1
a
outputs an output OUT
1
via the node N
4
that connects the P-type transistor
9
and the N-type transistor
5
with each other. A plurality of such option circuits are provided (for conveniences' sake,
FIG. 5
shows a case where two of the same are provided), and an option circuit
1
b
is designed so that program signals PRG
3
and PRG
4
are supplied to gates of the N-type transistors
6
and
7
, respectively, and that an output OUT
2
is outputted via the node N
4
that connects the P-type transistor
9
and the N-type transistor
5
with each other.
The following description will explain an operation in accordance with the foregoing arrangement. First of all, a case where this option circuit
1
a
is made to store a single bit will be explained below. Specifically, a case where a “0” state of binary logic is stored (programmed) by the option circuit
1
a
will be explained as an example of the operation.
All memory cells of the floating gate type (transistors
2
and
3
) inside the foregoing option circuit
1
a
are in a state of being erased by ultra violet (ultra-violet erasure), and their threshold voltages are neutralized to about 2V to 3V.
The bias voltage generation circuit
10
is normally designed to output the power source voltage Vcc, but an output of the bias voltage generating circuit
10
is set to as high as not lower than 10V, whereas a bias voltage outputted by the bias voltage generating circuit
11
is lowered to a Vss level, upon programming. This causes the N-type transistors
4
and
5
to be turned off, while only the program signal PRG
1
is raised to about 7V to 8V.
In this state, for a predetermined period of time, the program voltage VPRG (about 10V to 12V) is supplied to the drains of the N-type transistors
6
and
7
, but since the N-type transistor
7
is off while the N-type transistor
6
is on, a voltage of about 6V to 7V is applied to the drain side (the foregoing node N
1
) of the floating gate transistor
2
via the N-type transistor
6
.
This provides current flow between the drain and source of the floating gate transistor
2
. Hot electrons generated by the current are injected into a floating gate of the floating gate transistor
2
by a bias voltage (Vgate) applied to the floating gate transistor
2
. This causes the threshold voltage of the transistor
2
to increase. As a result, the threshold voltage is raised to about the power source voltage Vcc or above. On the other hand, the threshold voltage of the floating gate transistor
3
remains neutralized to about 2V to 3V. Thus, with a difference between the threshold voltages of the floating gate transistors
2
and
3
, the option circuit
1
is made to store “0”. This is identical to write-in to a common hot-electron-injected EPROM, flash memory, etc.
Next, a case where “1” is stored by the option circuit
1
a
will be explained below.
Only the program signal PRG
2
is set not lower than the power source voltage Vcc. In this state, for a predetermined period of time, the program voltage VPRG (about 10V to 12V) is supplied to the drains of the N-type transistors
6
and
7
. Since the N-type transistor
6
is off while only the N-type transistor
7
is on, a voltage of about 6V to 7V is applied to the drain side (the foregoing node N
2
) of the floating gate transistor
3
via the N-type transistor
7
. This provides current flow between the drain and source of the floating gate transistor
3
.
The threshold voltage of the transistor
3
is raised as is in the aforementioned case. On the other hand, the threshold voltage of the floating gate transistor
2
remains neutralized to about 2V to 3V. Thus, with a difference between the threshold voltages of the floating gate transistors
2
and
3
, the option circuit
1
a
is made to store “1”.
All the option circuits
1
a
in the CAM are subjected to the foregoing process before shipment of the device, so that either “0” or “1” is stored (programmed) in each.
Next, an operation in the case where the device is used by a user after shipment of the device thus programmed will be described below. For conveniences' sake, “0” is assumed to be stored (programmed) in the option circuit
1
a
. When the device is powered on, t
Ho Hoai V.
Morrison & Foerster / LLP
Sharp Kabushiki Kaisha
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