Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-04-20
2001-08-28
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185220, C365S185190
Reexamination Certificate
active
06282125
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention concerns a method for erasing and rewriting non volatile memory cells and particularly bilevel or multilevel flash cells.
2. Discussion of the Related Art
As known the operation of erasing in flash memories consists in extracting all the charges that are trapped in the floating gate of each cell by means of the application of one or more erasing pulses. This operation is carried out by applying a positive voltage on the source terminal, or in more sophisticated technologies, on the bulk one and a negative voltage (or null) on the gate in a such way so as to bring the value of the associated threshold voltage back to a low level and equal for all cells (erased level). The flash memory, for the way it is conceived, does not allow the erasing of the single cell, since in order to increase the cell density the source and bulk terminals of the single cells are shared. At the current state of the art the matrix of the flash memory is divided into sectors, each one of which is erasable independently from the others.
On the other hand, after the erasing operation, in order to allow a correct data storage operation, in particular if the memory is of multilevel type, it is necessary, in first place not to get any cell in depletion (too low threshold) and, in second place, that at the end of the process, all cells have a threshold voltage lower than a certain value (otherwise it would be confused with the first useful level). In addition, at the end of the process, all the thresholds of the cells to be erased must be within a not too wide interval of values.
However the presence from cells that, at each erasing pulse, modify their threshold voltage too little (slow in erasing cells) and of cells that modify it in an excessive way (fast in erasing cells), in addition to cells that behave in a correct way, does not allow to meet the above indicated requirements.
At present the operation of erasing is carried out by providing pulses with a preset length that are followed by a stage of verification of the erasing on all cells of the sector to be erased, or at least on a subset of cells (usually, all belonging to a entire row of the sector on which the operation is carried out), if particular circuit solutions that allow the selective erasing of a subset of cells are used. If only one cell of the sector or of the subset (that is of the row) in question does not pass the stage of verification because it has a threshold higher than a first preset value, a new pulse of erasing is given. When all cells of the sector or of the subset pass the stage of erasing the whole sector or subset is then controlled in order to verify that the thresholds are not lower than a second preset value until a percentage near 100% (for instance 98%) with positive result is reached. At the end of the stage of erasing, a soft programming pulse for a determined time is given to all cells.
This method requires considerable time because, by doing so even one cell that is too slow to be erased influences the duration of the erasing of the entire block and in addition it has a disadvantage from the point of view of power consumption, since some energy is required in order to discharge and to reprogram, to the desired level, all cells of the flash memory.
SUMMARY OF THE INVENTION
In view of the state of the art above described an object of the present invention is to provide a method for erasing memory cells that would allow a reduction of the erasing time and to save energy.
According to the present invention this and other objects are achieved by means of a method for erasing non volatile memories, particularly flash cells, that applies erasing pulses to the cells to be erased and verifies, after each pulse, the value of the threshold voltage of the cells. Said erasing pulses are provided to the cells as long as the respective values of the threshold voltage are greater than the new values of threshold voltage corresponding to new data to be rewritten in the cells to be erased.
Usually when erasing, the value that will have to be rewritten in the cell is not known and since the mechanism of programming can only increase the threshold, the starting point must be as low as possible.
In the case under examination that is not true any more, since for certain applications, the value to be rewritten is known beforehand. It is possible to take advantage of this through a statistic reasoning. In fact among the cells that must be reprogrammed some are at a lower level than the one to be reprogrammed at, and therefore these do not need to be erased, whereas other ones are at a slightly higher level than the one at which they must be reprogrammed, and therefore a partial erasing is necessary, other ones are exactly at the level at which they must be reprogrammed, and therefore no intervention must be carried out, and, finally, other ones (worst case), since they are at a higher level they must have the lowest level after the reprogramming stage.
Therefore part of the cells requires only a partial erasing unless all cells that are programmed at the highest logic level must be rewritten at the lowest logic level.
In this way in several cycles of erasing and rewriting, the distribution of the speed of erasing of the single cells as regards the required lowering of the threshold is half way between the worst case and the best case. This implies that the time necessary, for all the conditions to be met, is lower.
As a result of the present invention, a method for erasing and rewriting non volatile memory cells faster and less expensive in terms of energy than the traditional methods is provided.
REFERENCES:
patent: 5555204 (1996-09-01), Endoh et al.
Guaitini Giovanni
Pasotti Marco
Rolandi Pier Luigi
Galanthay Theodore E.
Hoang Huan
Morris James H.
STMicroelectronics S.r.l.
Wolf Greenfield & Sacks P.C.
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