Boots – shoes – and leggings
Patent
1993-03-26
1994-04-19
Mai, Tan V.
Boots, shoes, and leggings
36471501, G06F 750
Patent
active
053052498
ABSTRACT:
Arithmetic logic unit has an arithmetic logic circuit, an arithmetic circuit, and a selector which form a digital signal processor for processing video signals to be supplied to a display. The arithmetic logic circuit carries out one calculation selected from an addition of first and second input signals, a subtraction of the second input signal from the first input signal, and a subtraction of the first input signal from the second input signal, and the arithmetic circuit carries out a calculation selected from an addition of the first and second input signals and a subtraction of the first input signal from the second input signal. As a result of these calculations, the selector selects one of output signals of the arithmetic logic circuit and the arithmetic circuit. In this arithmetic logic unit, one of calculations of parallel addition and subtraction, addition and subtraction with selection, and absolute value of a difference is carried out.
REFERENCES:
patent: 3814925 (1974-06-01), Spannagel
patent: 4849921 (1989-07-01), Yasumoto et al.
patent: 4890251 (1989-12-01), Nitta et al.
patent: 4908788 (1990-03-01), Fujiyama
patent: 4953115 (1990-08-01), Kanoh
Mai Tan V.
NEC Corporation
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