Pulse or digital communications – Receivers – Angle modulation
Reexamination Certificate
1997-06-25
2001-07-17
Tse, Young T. (Department: 2634)
Pulse or digital communications
Receivers
Angle modulation
C375S324000, C375S332000, C329S304000
Reexamination Certificate
active
06263028
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an apparatus and method for measuring modulation parameters such as a transmitter gain A
0
, a droop factor (an amplitude variation per symbol) &sgr;
0
, a frequency error &OHgr;
0
, a phase error &thgr;
0
and I/Q origin offset B
0
in PSK, DPSK, QAM, GMS and similar quadrature-modulated wave signals modulated by digital data.
2. Description of the Related Art
Conventional apparatuses of this kind are disclosed, for example, in U.S. Pat. Nos. 5,187,719 (issued Feb. 16, 1993) (see the disclosure associated with FIG. 15, in particular) and 5,590,158 (issued Dec. 31, 1996). In these apparatus the input modulated wave signal is converted or transformed into an intermediate frequency signal, which is then converted to a digital signal for measurement of the modulation accuracy of the modulated signal through digital processing. And the intermediate frequency signal converted to digital form is subjected to DFT (Discrete Fourier Transform) processing to determine what is called a clock delay that is a phase difference between a symbol in the modulated wave signal and a symbol clock for measuring the symbol, and the intermediate frequency signal is corrected through digital processing by an interpolation filter in accordance with the clock delay thus determined.
Conventionally, the clock delay is determined through DFT processing of the intermediate frequency signal, so that its sampling rate needs to be sufficiently high, for example, approximately 1 MHz so as to provide the clock delay with required accuracy. Because of such a high sampling rate, much time is spent in digital processing for passing the A/D converted intermediate frequency signal through an intermediate frequency band pass filter and this period of time needed is as long as about one-third the total amount of measuring time of the modulation accuracy measuring apparatus.
SUMMARY OF THE INVENTION
According to the present invention, the intermediate frequency signal converted into digital form is quadrature-converted and the converted output is then down converted by a decimation means to substantially the lowest sampling rate necessary for measurement, which is more than twice the frequency bandwidth of a base band signal that is the quadrature-converted output, about four times in view of design margin. From the output of the decimation means, a clock delay is detected by a clock delay estimate means through utilization of a variance method and the quadrature-converted output is corrected by a delay correct means by the detected clock delay to produce a signal for obtaining demodulated data.
More specifically, the quadrature-converted output is subjected to fast fourier transform processing, then a rough estimate of a frequency error is calculated from the result of transformation, and the quadrature-converted output is corrected corresponding to the thus calculated frequency error and fed to the decimation means.
The frequency error of the input quadrature-converted output is further detected by the clock delay estimate means, then the detected frequency error is corrected by a second frequency correct means with respect to the output of the decimation means, and the thus corrected output is fed to the delay correct means.
The signal corrected by the second frequency correct means is repeatedly fed back to the clock delay estimate means until the frequency error detected by the clock delay estimate means goes down below a predetermined value.
The clock delay estimate means also detects origin offset of the quadrature-converted output in the I/Q plane and corrects its origin offset accordingly, the thus corrected quadrature-converted output is fed to the delay correct means.
The delay correct means includes also a decimation means that outputs only data at symbol points.
An error vector is computed from the output signal of the delay correct means and an ideal signal. The error vector is repeatedly calculated with the corrected delay by the delay correct means slightly varied so that the error vector is minimized.
REFERENCES:
patent: 5187719 (1993-02-01), Birgenheier et al.
patent: 5590158 (1996-12-01), Yamaguchi et al.
patent: 5640416 (1997-06-01), Chalmers
John G. Proakis, Digital Communications, Second Edition, McGraw-Hill, pp. 164-165, 302-303.
R.W. Hamming, Digital Filters, Prentice-Hall, pp. 48-49.
Advantest Corporation
Staas & Halsey , LLP
Tse Young T.
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