Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
1999-12-23
2001-04-03
Nelms, David (Department: 2818)
Static information storage and retrieval
Interconnection arrangements
C365S230060, C365S069000
Reexamination Certificate
active
06212090
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device including a repetitive pattern and, more specifically, to a dynamic semiconductor device (DRAM) including a repetitive pattern such as a word-line driving circuit.
This application is based on a Japanese Patent Application No. 10-369282 filed Oct. 25, 1998, the contents of which is incorporated herein by reference.
Recently DRAMs have been decreased greatly in size of element structure. In particular, word lines for selecting memory cells arranged in a memory cell array are formed under design rules. The width of one word line and the interval between adjacent word lines are decreased further. Moreover, a word-line driving circuit for selectively driving such a word line needs to be disposed in a narrow area. Some prior art methods have been therefore developed.
FIGS. 1
to
3
each illustrate a relationship between word lines and word-line driving circuits as one of the prior art methods. In
FIG. 1
, word-line driving circuits
210
connected to their respective word lines WL
0
, WL
1
, . . . , are arranged on one side of a memory cell array (MCA)
211
. In the actual pattern layout, a word-line driving circuit is difficult to dispose between fine word lines. It is thus thought that the word-line driving circuits
210
are arranged on either side of the memory cell array
211
as shown in
FIGS. 2 and 3
.
FIG. 2
is directed to a method of driving adjacent word lines alternately one by one by means of the word-line driving circuits
210
arranged on both sides of the memory cell array
211
.
FIG. 3
is directed to a method of driving adjacent word lines alternately two by two by means of the word-line driving circuits
210
arranged on both sides of the memory cell array
211
. Of the above three methods shown in
FIGS. 1
to
3
, an appropriate one to be processed the most easily is selected according to a process technique such as lithography and etching.
When the word-line driving circuits are arranged as shown in
FIGS. 1
to
3
, a plurality of word-line driving circuits corresponding to a plurality of word lines are combined into one repetitive unit. A plurality of such repetitive units are arranged. In a normal DRAM, word lines are selected by decoding a low-order n bit (n≧1) input address. One repetitive unit therefore coincides with 2
n
word lines. Assuming that an input address is two bits of A
1
and A
0
, the word-line driving circuits connected to four word lines corresponding to logical values (0, 0), (0, 1), (1, 0) and (1, 1) of (A
1
, A
0
), constitute one repetitive unit.
FIGS. 4 and 5
show a circuit arrangement of the above repetitive unit and a layout of wires. Referring to these figures, word-line driving circuits
210
(referred to as word-line decoders hereinafter) are each constituted of a NAND circuit
210
a
and an inverter circuit
210
b.
A first metal wiring layer M
1
is connected to an input terminal of the NAND circuit
210
a.
Address signals (low-order bits of an input address) A
0
, /A
0
, A
1
and /A
1
(/ indicates an inverted signal) are supplied to a plurality of second metal wiring layers M
2
formed above the first metal wiring layer M
1
. These layers M
1
and M
2
are connected by a contact CT located in a desired position. The high-order bit of the input address is supplied to the input terminal of the NAND circuit
210
a
, but its description is omitted for simplification.
BRIEF SUMMARY OF THE INVENTION
For DRAMs, it is desired that the chip area can be decreased as much as possible to lower manufacturing costs. In particular, a reduction in the area of a word-line decoder including a plurality of repetitive units having the same arrangement is very important in view of a reduction in the area of the entire chip. It can be thought that adjacent repetitive units have a contact and a wiring layer in common in order to reduce the area of a word-line decoder. In the layout shown in
FIG. 5
, it is difficult to share a contact with adjacent repetitive units.
More specifically, as illustrated in
FIG. 6
, when a plurality of repetitive units A and B are arranged adjacent to each other, the locations of contacts CT
1
and CT
2
on the boundary portions of the units A and B differ from each other. In other words, the contact CT
1
on the boundary portion of the repetitive unit A is connected to a wiring layer M
2
supplied with an address signal /A
0
, while the contact CT
2
on the boundary portion of the repetitive unit B is connected to a wiring layer M
2
supplied with an address signal A
1
. It is thus difficult to share the contacts CT
1
and CT
2
with the repetitive units A and B. In
FIG. 6
, word-line decoders for selecting word lines WL
1
and WL
2
in both the repetitive units A and B, are omitted.
As described above, in the prior art semiconductor device, adjacent repetitive units cannot have a contact located on a boundary portion therebetween in common. It was therefore difficult to reduce the layout area of a word-line decoder, with the result that neither the chip area nor the manufacturing costs could be decreased.
Accordingly, the object of the present invention is to provide a semiconductor device capable of decreasing in chip area and manufacturing costs.
To attain the above object, according to a first aspect of the present invention, there is provided a semiconductor device comprising a first repetitive unit including a plurality of decoders for selecting at least two wires, and a second repetitive unit whose arrangement is equal to that of the first repetitive unit and which is arranged adjacent to and symmetrically with the first repetitive unit, the first and second repetitive units having a wire and a contact, which are located on a boundary portion of the first and second repetitive units, in common.
According to a second aspect of the present invention, there is provided a semiconductor device comprising a first repetitive unit including a plurality of decoders for selecting a word line, a plurality of input wires of each of the decoders being connected to a plurality of address wires, and a second repetitive unit arranged symmetrically with and adjacent to the first repetitive unit and having a plurality of decoders for selecting a word line, a plurality of input wires of each of the decoders being connected to a plurality of address wires, wherein the first and second repetitive units have an input wire of the decoders and a contact between the input wire and the address wire, which are located on a boundary portion of the first and second repetitive units, in common.
According to a third aspect of the present invention, there is provided a semiconductor device comprising a decoder for outputting a plurality of word-line driving voltages in accordance with an address signal, a plurality of wires connected to the decoder and supplied with the plurality of word-line driving voltages, a first repetitive unit including a plurality of driving circuits whose output terminals are connected to word lines and connected to the plurality of wires, and a second repetitive unit including a plurality of driving circuits whose output terminals are connected to word lines and contacts connected to the plurality of wires, the contacts of the second repetitive unit being arranged symmetrically with contacts of the first repetitive unit, wherein driving circuits located on a boundary portion between the first and second repetitive units have a contact connected to one of the plurality of wires in common.
The semiconductor device of the present invention enables adjacent first and second repetitive units to have an element on a boundary portion therebetween in common. An area for arranging the first and second repetitive units can thus be reduced.
Moreover, in one of the first and second repetitive units, when the output terminals of adjacent decoders are connected to cross each other, the internal wires of adjacent decoders are connected to cross each other, the input terminals of adjacent decoders are connected to cross each other, both
Akita Hironobu
Kohno Fumihiro
Shiratake Shinichiro
Banner & Witcoff , Ltd.
Kabushiki Kaisha Toshiba
Le Thong
Nelms David
LandOfFree
Semiconductor device including a repetitive pattern does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device including a repetitive pattern, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device including a repetitive pattern will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2549693