Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
1999-11-08
2001-07-10
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Multiple values
C365S185020, C365S185120
Reexamination Certificate
active
06259624
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor storage device and a data writing method thereof. In particular, the present invention relates to a multi-value type nonvolatile semiconductor storage device of which each memory cell stores multi-value data of two bits or more and a data writing method thereof.
2. Description of the Related Art
In recent years, flash memories are becoming common as record mediums for use with video/audio units and portable information units because of their higher electric characteristics than those of conventional various record units and hard disk units. A flash memory is a rewritable nonvolatile semiconductor storage device. With respect to connection and structure of flash memories, they can be roughly categorized as NOR type and NAND type. Conventional nonvolatile semiconductor storage devices such as memories are normally two-value type devices of which each memory cell stores data of two values “0” and “1”. However, recently, as large storage capacities of semiconductor storage devices are being required, a so-called multi-value type nonvolatile semiconductor storage device of which each memory cell stores multi-value data of three values or more (two bits or more) has been proposed.
As examples of such multi-value type nonvolatile semiconductor storage devices, a four-value type NAND flash memory and an eight-value type NAND flash memory are known. In the four-value type NAND flash memory, each memory cell transistor stores data of two bits that represents four values. In the eight-value type NAND flash memory, each memory cell transistor stores data of three bits that represents eight values.
FIG. 1
is a graph showing the relation between distributions of threshold voltages Vth and data of memory cell transistors of an eight-value type NAND flash memory. In
FIG. 1
, the vertical axis represents threshold voltages Vth of memory cell transistors, whereas the horizontal axis represents distributions of the threshold voltages Vth of the memory cell transistors.
As shown in
FIG. 1
, in the eight-value type NAND flash memory, the threshold voltages Vth of the memory cell transistors are in eight states (distribution
7
to distribution
0
) corresponding to data “000”, “001 ”, “010”, “011”, “100”, “101”, “110”, and “111”, respectively. In
FIG. 1
, VVF
1
, VVF
2
, VVF
3
, VVF
4
, VVF
5
, VVF
6
, and VVF
7
represent voltages of selected word lines in verifying operations corresponding to these states. On the other hand, VRD
1
, VRD
2
, VRD
3
, VRD
4
, VRD
5
, VRD
6
, and VRD
7
represent voltages of selected word lines in normal reading operations corresponding to these states. The voltages of the selected word lines have the relation of VVF
7
>VRD
7
>VVF
6
>VRD
6
>VVF
5
>VRD
5
>VVF
4
>VRD
4
>VVF
3
>VRD
3
>VVF
2
>VRD
2
>VVF
1
>VRD
1
. For example, VVF
7
=3.8 V, VRD
7
=3.6 V, VVF
6
=3.2 V, VRD
6
=3.0 V, VVF
5
=2.6 V, VRD
5
=2.4 V, VVF
4
=2.0 V, VRD
4
=1.8 V, VVF
3
=1.4 V, VRD
3
=1.2 V, VVF
2
=0.8 V, VRD
2
=0.6 V, VVF
1
=0.2 V, VRD
1
=0 V.
However, in multi-value type NAND flash memories, as a method for writing data to memory cells, multi-value data is written at a time (in parallel) in such a manner that the voltage of bit lines is varied corresponding to write data. This method is referred to as multi-value parallel writing method and used to speed up the writing operations. In the case of an eight-value type NAND flash memory, ideally, as shown in column (a) of
FIG. 1
, when the voltage of the bit line for write data “000” is set to 0 V, the voltage of the bit line for write data “001” is set to 0.6 V, the voltage of the bit line for write data “010” is set to 1.2 V, the voltage of the bit line for write data “011” is set to 1.8 V, the voltage of the bit line for write data “100” is set to 2.4 V, the voltage of the bit line for write data “101” is set to 3.0 V, the voltage of the bit line for write data “110” is set to 3.6 V, the voltage of the bit line for write data “111” is set to 8.0 V, then all data in different write levels can be written almost at the same time.
However, from view points of low power consumption and low device area, a so-called self-boost method or local self-boost is used.
Next, with reference to
FIG. 2
, a self-boost writing method will be described. A memory cell of an NAND flash memory is composed of a MOS transistor having a floating gate (FG) and a control gate (CG). A predetermined number of the same memory cell transistors are connected in series as a memory string. In a memory array of the NAND flash memory, a plurality of memory strings are disposed in parallel. In the memory array, memory cell transistors on the same line are connected with a common word line. In the example shown in
FIG. 2
, one memory string is composed of eight memory transistors M
0
to M
7
connected in series. One end of the memory string (namely, the drain of a memory cell transistor M
7
) is connected to a bit line BL through a selected transistor DS. The other end of the memory string (the source of a memory transistor M
0
) is connected to a source line SL through a selected transistor SS. The control gates of the memory cell transistors M
0
to M
7
are connected to the word lines WL
0
to WL
7
, respectively. The gate of the selected transistor DS is connected to a drain side selected transistor SS. The gate of the selected transistor SS is connected to a source side selected gate line SSG.
In the self-boost writing method, the signal level of the drain side selected gate line DSG is set to Vcc. In addition, the signal level of the source side selected gate line SSG is set to GND. When a memory string is selected corresponding to an address decode signal, the voltage of bit lines connected to the selected memory string is set to VBL corresponding to write data. The voltages of bit lines connected to memory strings that have not been selected are kept in a pre-charge level (i.e., in a floating state). Thereafter, the voltage of the selected word line as a write page (in this example shown in
FIG. 2
, the word line is WL
4
) is set to a predetermined write voltage VPGM. The voltage of the other non-selected word lines is set to a write pass voltage Vpass (<VPGM). Thus, data is written to write memory cell transistors.
At this point, channels of memory cell transistors whose write data is the same as erase state (namely, the write data is “111”) and channels of non-selected memory cell transistors of the memory string are disconnected from the relevant bit lines BL by the drain side selected transistor DS. The voltages of the memory cell transistors are boosted to a non-write voltage by a coupling connection with word lines, and mainly, non-selected word lines.
However, in the self-boost writing method or local-boost writing method, since the signal level of the drain side selected gate line DSG is set to VCC, the voltage supplied to channels of memory cell transistors of the memory string through the bit lines BL is limited to V
cc
—VthDSG (where VthDSG is a threshold voltage of the selected transistor DS) by the drain side selected transistor DS of the memory string. Thus, when data is written, the upper limit of the voltage supplied to the bit lines BL is V
cc
—VthDSG with a margin (for example, 1.5 V).
In a multi-value type NAND flash memory, from a viewpoint of a write speed, it is preferred that the voltage of bit lines is set corresponding to write data in the relation of 1 to 1. However, in an eight-value type NAND flash memory, eight-value latch circuits should be disposed corresponding to the number of bit lines. Thus, actually, the voltage of bit lines for write data “00x” (where x is 0 or 1) is set to 0 V, the voltage of bit lines for write data “01x” (where x is 0 or 1) is set to VB
1
, the voltage of bit lines for write data “1x” (where x is 0 or 1) is set to VB
2
, the voltage of bit lines for write data
Kananen Ronald P.
Lam David
Nelms David
Rader Fishman & Grauer
Sony Corporation
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