Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Software program
Reexamination Certificate
1995-10-18
2001-01-09
Teska, Kevin J. (Department: 2763)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Software program
C703S020000, C716S030000, C716S030000
Reexamination Certificate
active
06173245
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to programmable logic array integrated circuit devices, and more particularly to the design of logic for implementation in such devices.
Programmable logic array integrated circuit devices are well known as shown, for example, by Wong et al. U.S. Pat. No. 4,871,930, Cliff et al. U.S. Pat. No. 5,260,611, and commonly assigned, co-pending U.S. patent application Ser. No. 08/442,795, filed May 17, 1995, all of which are hereby incorporated by reference herein. Such devices typically include a large number of relatively small logic modules, each of which is programmable to perform any of several logic functions on signals applied to that logic module. The modules are interconnectable in various ways by a programmable network of interconnection conductors so that the relatively simple logic functions performed by the individual logic modules can be concatenated into much more complex logic functions.
Computer programs are well known for assisting a user of a programmable logic device in implementing a desired logic design in the device. An example of such a computer program is the MAX+PLUS II Programmable Logic Development System, which is commercially available from Altera Corporation of San Jose, Calif. The MAX+PLUS II system is described, for example, in the Altera publications “MAX+PLUS II Getting Started”, Version 5.0, July 1994, and “MAX+PLUS II AHDL”, Version 5.0, July 1994, both of which are hereby incorporated by reference herein. The MAX+PLUS II system allows the user to specify the desired logic on a computer (e.g., an IBM-compatible personal computer with an Intel 486 microprocessor and adequate memory) using any of several different logic description interfaces. For example, there are text-based interfaces such as the Altera Hardware Description Language (“AHDL”), and there are graphics-based interfaces such as the MAX+PLUS II Graphic Editor. These interfaces allow the user to specify the desired logic in generic terms that are relatively standard for logic design and convenient for the user. They are not specific to the characteristics of the particular programmable logic device to be used.
Once the user has specified the desired logic design, computer programs such as the MAX+PLUS II system automatically convert that design to the form required for implementation on a particular programmable logic device. This typically involves reducing the user's logic design to relatively small pieces of logic (e.g., individual gates and flip-flops) that can be implemented in the logic modules of the device, and identifying the connections through the interconnection conductor network that are needed to interconnect the modules in the way required to produce the user's logic design. This process is sometimes referred to as “compilation” of the user's logic design. The computer program may then go on to control a device programmer to actually program the device (i.e., by programming the logic modules of the device to perform the various pieces of logic mentioned in the preceding sentence, and by programming the interconnection conductor network of the device to make the necessary connections between the logic modules).
As programmable logic devices have become larger (not necessarily in the physical sense but in the sense of increased logic capacity) and therefore capable of implementing more complex logic designs, a need has developed for more sophisticated user logic design and implementation tools. For example, an industry-standard “Library of Parameterized Modules” (LPM) has been developed in which various types of logic components are generalized in terms of one or more variables or “parameters.” Thus a counter may be described generally using a parameter for its ultimate capacity, rather having different specifications for counters of different capacity (e.g., 2-bit, 4-bit, 6-bit, 8-bit, etc., capacity). Another parameter for a counter may indicate whether it counts up or down. An AND gate or multiplexer may be generalized using a parameter for its number of inputs. Parameterizing logic modules helps a logic designer in a number of ways, e.g., by facilitating re-use in different contexts of logic that the designer has already designed or that is otherwise extent. It would therefore be desirable for computer programs such as the MAX+PLUS II system to be able to support such parameterization.
In view of the foregoing, it is an object of this invention to provide improved methods for designing or specifying logic to be implemented in a programmable logic device.
It is a more particular object of this invention to provide programmable logic device logic implementation methods which allow the user to specify the desired logic design at least partly in terms of parameterized logic modules.
SUMMARY OF THE INVENTION
These and other objects of the invention are accomplished in accordance with the principles of the invention by providing programmable logic device logic implementation methods which allow the user to specify the desired logic in parameterized terms. Preferably the methods of this invention permit specific values to be assigned to each parameter in any of several different ways (e.g., “globally” (covering all instances of a logic module unless superseded as described below), “sub-globally” (covering all instances of a logic module from a particular instance of the module down through the remainder of all dependent branches in the hierarchy of the logic design, again unless superseded by a further sub-global parameter specification), or “by default”). Associated with this feature, the methods of this invention preferably follow particular rules for the selective “inheritance” of specific values for parameters from module to module as one moves down through the hierarchy of the logic design. For example, a specific value for a logic module parameter specified sub-globally at any point in the hierarchy of the logic design is inherited by all logic module instances in the hierarchy below the point at which that value is specified, unless that inheritance is cut off at some point by sub-globally setting another specific value for that parameter. Global values are inherited by all logic module instances in the design unless that inheritance is cut off by a sub-global specification of a different parameter value. Default values are used only in an instance of the logic module in which they are specified, if those parameters are otherwise unspecified globally or sub-globally in the hierarchy above that logic module instance. Default values are not passed on to other logic modules by inheritance.
During processing of the data for a user's logic design in accordance with this invention the specific values associated with each parameter of a parameterized logic module are preferably not associated with any instance of the logic module until relatively late in the process. For example, not until compilation of a particular instance of a logic module are the particular parameter values to be used for that instance of that module determined and used in the compilation process. Prior to such compilation, the data for each instance of a parameterized logic module is kept in general (“parameterized”) form. This facilitates manipulation of the parameterized modules, identification of module instances that are either identical to other instances (because all the parameter values are the same) or different from one another (because one or more parameter values are different), etc. When multiple instances of a parameterized logic module are thus found to be identical, the compilation process can be significantly shortened because data from an earlier compilation of the module can simply be copied. Moreover, in doing such copying, it does not matter that the copied data includes parameterized sub-modules that may ultimately turn out to have different parameter values in different instances. This is so because, as mentioned above, the sub-module parameter information is still general
Chen Jeffrey
Karchmer David
Redman Scott D.
Schleicher James
Altera Corporation
Fish & Neave
Jackson Robert R.
Phan Thai
Shanahan Michael E.
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