Output buffer circuit with preset function

Details Output buffer circuit with preset function Output buffer circuit with preset function

1999-12-29

2001-04-03

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C327S374000, C327S384000

Reexamination Certificate

active

06211707

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to an output buffer circuit in a semiconductor memory device, and more particularly to an output buffer circuit with a preset function for precharging a voltage level of an output pad at a constant level before the next output signal is provided to the output pad to improve data access speed and to reduce noise.
An output buffer circuit in a semiconductor memory device outputs an output signal from a sense amplifier to an output pad and the prior output buffer circuit is shown in FIG.
1
. Referring to
FIG. 1
, the prior output buffer circuit includes a first two-input NAND gate
11
receiving a control signal poe which is an enable signal as a first input signal and an input signal sj from a sense amplifier (not shown) as a second input signal to generate a pull up driving signal dp; a first inverting gate
12
for inverting the input signal sj; a second two-input NAND gate
13
receiving an output signal of the first inventing gate
12
as a first input signal and the control signal poe as a second signal; a second inverting gate
14
for inverting an output signal of the second NAND
12
to generate a pull down driving signal dn; a PMOS transistor
15
being driven by the pull up driving signal dp from the first NAND gate
11
; and a NMOS transistor
16
being driven by the pull down driving signal dn. The output buffer circuit generates an output signal out through drains of the PMOS transistor
15
and the NMOS transistor
16
which are commonly connected to each other.
Hereinafter, the operation of the output buffer circuit in
FIG.1
will be described with reference to
FIG. 2A
to
FIG. 2C
in more detail. If the control signal poe, that is an enable signal is a high state as shown in
FIG. 2A
, the output buffer circuit is enabled and the level of the output node OUT is determined in accordance with a logic state of the input signal sj. That is, if the input signal sj is a high state, the pull up driving signal dp and the pull down driving signal dn become all low states. The pull up transistor, the PMOS transistor
15
is turned on and the pull down transistor, the NMOS transistor
16
is turned off, so that the output node becomes a high state. If the input signal sj is a low state as shown in
FIG. 2
b
, the pull up driving signal dp and the pull down driving signal dn are all high states. The PMOS transistor
15
is turned off and the NMOS transistor
16
is turned on, so that the output node OUT becomes a low state as shown in FIG.
2
C.
On the contrary, if the control signal poe is a low state as shown in
FIG. 2A
, the output buffer circuit is disabled. If the output buffer circuit becomes disabled, the pull up driving signal becomes a high state and the pull down driving signal becomes a low state. The PMOS transistor
15
and the NMOS transistor
16
are turned off and the output node is floating and then is transited into a high impedance as shown in FIG.
2
C.
However, when the capacitance of a load capacitor in the output node is large, next data is generated before the output node is transited into a high impedance and the time for charging and discharging the load capacitor is required so that the access time is increased. Accordingly, the swing of the output signal becomes large to increase current noise.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a data output buffer for reducing a data access time and noise by precharging an output node to a constant level in disable.
There is provided to a data output buffer having an input pad and an output pad, comprising: output driver means for buffering an output of a sense amplifier through the input pad and providing it to the output pad in accordance with a control signal, the output driver means including a pull up driver and a pull down driver; voltage level detection means for receiving data fed back from the output pad and comparing the data and a reference voltage level in accordance with the control signal and a chip select signal; preset signal generation means for receiving the control signal to control an output driver control means; and the output driver control means for receiving output signals from the voltage level detection means and the preset signal generation means to control the output driver means.
The output driver means includes: a pull up/down driver portion for buffering the output signal of the sense amplifier, the pull up/down driver portion including the pull up derive and the pull down driver; and a control portion for controlling the pull up/down driver portion by the control signal. The control portion includes: a first NAND gate for receiving the control signal and the output signal from the sense amplifier; and a first inverting gate for inverting an output signal of the first NAND gate; a second inverting gate for inverting the output signal from the sense amplifier; and a second NAND gate for receiving an output signal of the second inverting gate and the control signal. The pull up/down driver portion includes a PMOS transistor and a NMOS transistor, respectively.
The voltage level detection means includes: an output voltage detection portion for receiving the data fed back from the output pad to generate a voltage level detection signal to the output driver control means; and a control portion for controlling the output voltage detection portion for receiving the chip selection signal and the control signal to enable the output voltage detection portion when the data output buffer is disabled.
The control portion for controlling the output voltage detection portion includes: a NOR gate for receiving the control signal and the chip selection signal; and a first inverting gate for inverting an output signal of the NOR gate.
The output voltage detection portion includes; a first PMOS transistor where the output pad is connected to a source and an output signal of the first inverting gate is applied to a gate; a second PMOS transistor where a drain of the first PMOS transistor is connected to a source; a resistor where one terminal is connected to a gate and a drain of the second PMOS transistor and another terminal is grounded; a second inverting gate for receiving a voltage divided by the resistor and the first and second PMOS transistors to generate the voltage level detection signal; and a condenser being connected between an output of the second inverting gate and a ground.
The preset signal generation means includes: first delay means for delaying the control signal for a first selected time when the control signal becomes a first voltage level; second delay means for delaying the control signal for a second selected time longer than the first time to generate an inverted delayed control signal when the control signal becomes a first voltage level before it becomes a second level; and a NOR gate for receiving output signals from the first and second delay means to generate a logic-NORed edge signal.
The output driver control means includes: a pull up driver control portion for controlling the pull up driver to supply a power voltage to the output pad during a pulse of the output signal generated from the preset signal generation means, if the voltage level of the output pad detected through the voltage level detection means, is lower than the reference voltage level when the output buffer is disabled; and a pull down driver control portion for controlling the pull down driver to supply a ground voltage to the output pad during the pulse generated from the preset signal generation means, if the voltage level of the output pad detected through the voltage level detection means, is higher than the reference voltage level when the output buffer is disabled. The pull up driver control portion includes; a first NAND gate for receiving the output signals from the voltage level detection means and the preset signal generation means; a first inverting gate for inverting an output signal of the first NAND gate; and a NOR gate for receiving output signals from the first inverting gate and the pull

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