Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-07-02
2001-07-17
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S707000, C438S710000, C438S305000, C438S597000, C438S637000, C438S439000
Reexamination Certificate
active
06261965
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device and, more particularly, to a manufacturing method of a contact hole or an FET having an LDD structure.
2. Description of Related Art
In recent years, contact holes or the like with higher aspect ratios have been in demand mainly due to the increasing microminiaturization of semiconductor integrated circuits.
Contact holes are usually formed by etching insulating films by using resists or the like as masks. When a contact hole with a high aspect ratio is formed by dry etching, the pressure in the etching process is decreased in order to achieve a normal configuration and a higher selection ratio of the contact hole. To obtain the high selection ratio, a C-rich fluorocarbon gas is employed.
Using the C-rich forms a SiC layer on the surface of a silicon substrate in some cases. The SiC layer inhibits oxidation of silicon; therefore, it cannot be eliminated by a technique based on the standard sacrificing oxidation and HF etching. Further, the high resistance of the SiC layer inevitably results in an increased contact resistance because of the formed SiC layer. Hitherto, therefore, the SiC layer has been removed by isotropic radical etching that uses CF
4
, SF
6
or the like.
The problem of the undesirable formation of the SiC layer has been occurring also in the forming process of transistors or an element separating process. The etching technique using CF
4
, SF
6
or the like has been posing a problem because of its high etching speed, in which the underlayer, namely, the silicon layer, is undesirably etched in an attempt to remove only the SiC layer. There has been another problem in that, because the SiC layer is not usually formed evenly, the silicon underlayer in a thinner portion of the SiC layer is etched more deeply, resulting in a rough surface.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a manufacturing method of a semiconductor device that permits effective removal of a SiC layer. The manufacturing method of a semiconductor device in accordance with the present invention has a step for removing a silicon carbide layer formed on a silicon substrate by plasma treatment using a gas that contains hydrogen.
REFERENCES:
patent: 4283249 (1981-08-01), Ephrath
patent: 5180466 (1993-01-01), Shin
patent: 5591664 (1997-01-01), Wang et al.
patent: 5723383 (1998-03-01), Kosugi et al.
patent: 5998302 (1999-12-01), Fujisawa
“A General Mechanism and Dissolution Technique of Oxidation Retardation Layer” by Sumio Sekiyama, Yoshikazu Motoyama, Kenya Iwasaki, Kouichirou Inazawa and Shigeyoshi Kojima, which was starting at p. 355 of Proceedings of symposium on dry process which was held at Waseda University in Nov., 1997.
Bowers Charles
Mimura Junichi
OKI Electric Industry Co., Ltd.
Smoot Stephen W.
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