Pipelined Microprocessor and load address prediction method ther

Details Pipelined Microprocessor and load address prediction method ther Pipelined Microprocessor and load address prediction method ther

1996-11-01

1999-05-11

Coleman, Eric

39580024, 39580028, 39580041, G06F1/00

Patent

active

059037687

ABSTRACT:
A pipelined microprocessor is a capable of avoiding pipeline stalls caused by data hazards in which a load instruction information registration section 1 registers information relating to load instructions into a load instruction information storing section 3 in advance, an address calculation section 3 calculates a predicted load address before accessing a load address obtained by executing the load instruction by a pipeline processing section, a calculation result judgement section 7 judges whether or not the predicted load address is correct. Thereby, following instructions will use data as the execution result of the load instruction.

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Golden et al., "Hardware Support for Hiding Cache Latency", University of Michigan Technical Report, pp. 3-21, Jan. 13, 1995.
Eickemeyer et al., "A load-instruction unit for pipelined processors", IBM J. Res. Develop, vol. 37, No. 4, pp. 547-564, Jul. 4, 1993.
Austin et al., "Zero-Cycle Loads: Microarchitecture Support for Reducing Load Latency", Proceedings of the 28th Annual International Symposium on Microarchitecture.

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