Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1996-09-27
2001-03-13
Nguyen, Chanh (Department: 2675)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S103000
Reexamination Certificate
active
06201521
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates to image display systems using spatial light modulators (SLMs), and more particularly to the organization of display elements on the SLM and to methods of addressing display elements of the SLM with data.
BACKGROUND OF THE INVENTION
Video display systems based on spatial light modulators (SLMs) are increasingly being used as an alternative to display systems using cathode ray tubes (CRTs). SLM systems provide high resolution displays without the bulk and power consumption of CRT systems.
Digital micro-mirror devices (DMDs) are a type of SLM, and may be used for either direct-view or projection display applications. A DMD has an array of micro-mechanical display elements, each having a tiny mirror that is individually addressable by an electronic signal. Depending on the state of its addressing signal, each mirror tilts so that it either does or does not reflect light to the image plane. The mirrors may be generally referred to as “display elements”, which correspond to the pixels of the image that they generate. Generally, displaying pixel data is accomplished by loading memory cells connected to the display elements. The display elements can maintain their on or off state for controlled display times.
Other SLMs operate on similar principles, with an array of display elements that may emit or reflect light simultaneously, such that a complete image is generated by addressing display elements rather than by scanning a screen. Another example of an SLM is a liquid crystal display (LCD) having individually driven display elements.
To achieve intermediate levels of illumination, between white (on) and black (off), pulse-width modulation (PWM) techniques are used. The basic PWM scheme involves first determining the rate at which images are to be presented to the viewer. This establishes a frame rate and a corresponding frame period. For example, in a standard television system, images are transmitted at 30 frames per second, and each frame lasts for approximately 33.3 milliseconds. Then, the intensity resolution for each pixel is established. In a simple example, and assuming n bits of resolution, the frame time is divided into 2
n
-1 equal time slices. For a 33.3 millisecond frame period and n-bit intensity values, the time slice is 33.3/(2
n
-1) milliseconds.
Having established these times, for each pixel of each frame, pixel intensities are quantized, such that black is 0 time slices, the intensity level represented by the LSB is 1 time slice, and maximum brightness is 2
n
-1 time slices. Each pixel's quantized intensity determines its on-time during a frame period. Thus, during a frame period, each pixel with a quantized value of more than 0 is on for the number of time slices that correspond to its intensity. The viewer's eye integrates the pixel brightness so that the image appears the same as if it were generated with analog levels of light.
For addressing SLMS, PWM calls for the data to be formatted into “bit-planes,” each bit-plane corresponding to a bit weight of the intensity value. Thus, if each pixel's intensity is represented by an n-bit value, each frame of data has n bit-planes. Each bit-plane has a 0 or 1 value for each display element. In the simple PWM example described in the preceding paragraphs, during a frame, each bit-plane is separately loaded and the display elements are addressed according to their associated bit-plane values. For example, the bit-plane representing the LSBs of each pixel is displayed for 1 time slice, whereas the bit-plane representing the MSBs is displayed for 2n/2 time slices. Because a time slice is only 33.3/(2
n
-1) milliseconds, the SLM must be capable of loading the LSB bit-plane within that time. The time for loading the LSB bit-plane is the “peak data rate.” U.S. Pat. No. 5,278,652, entitled “DMD Architecture and Timing for Use in a Pulse-Width Modulated Display System,” assigned to Texas Instruments Incorporated describes various methods of addressing a DMD in a DMD-based display system. These methods are directed to loading data at the peak data rate. In one method, the time in which the most significant bit is displayed is broken into smaller segments so that loading for less significant bits can occur during these segments. Other methods involve clearing the display elements and using extra “off” times to load data.
Another method of solving the peak data rate problem is referred to as “memory multiplexing” or “split reset.” This method uses a specially configured SLM, whose display elements are grouped into reset groups that are separately loaded and addressed. This reduces the amount of data to be loaded during any one time, and permits the LSB data for each reset group to be loaded at a different time during the frame period. This configuration is described in U.S. patent Ser. No. 08/300,356, entitled “Pixel Control Circuitry for Spatial Light Modulator”, assigned to Texas Instruments Incorporated.
SUMMARY OF THE INVENTION
One aspect of the invention is a method of loading pixel data to memory cells of a spatial light modulator (SLM) having individually addressable display elements, for a pulse width modulated display. The data is received as a series of frames of data. Each frame is formatted into bit-planes, each bit-plane having one bit of data for each display element, and each bit-plane representing a bit-weight of intensity values to be displayed by the display elements, and each bit-plane having a display time corresponding to its bit-weight. The bit-planes are then divided into reset groups of data, each reset group representing data for a reset group of display elements connected to a common reset line. The memory cells of each reset group of display elements are loaded with reset groups of data, such that after the memory cells of one reset group are loaded with data of one bit-plane, different memory cells of a next reset group are loaded with other data of that bit-plane. Reset groups of display elements that are not currently being loaded can be reset (allowed to change state) while other reset groups are being loaded.
A technical advantage of the invention is that it provides a loading method that reduces the peak data rate by allowing simultaneous reset and loading operations. Less data is required to be loaded in one load cycle, as compared to “global reset” methods, in which the entire SLM array is loaded in one load cycle. Furthermore, bit-planes can be displayed for shorter times without loss of brightness that occurs when all display elements must be shut off while memory loading occurs. Finally, although it requires more memory cells than split reset methods, it does not require that reset groups be arranged in an interleaved pattern, which can lead to visual artifacts.
REFERENCES:
patent: 5278652 (1994-01-01), Urbanus et al.
patent: 5612713 (1997-03-01), Bhuva et al.
patent: 5657036 (1997-08-01), Markandey et al.
patent: 5706123 (1998-01-01), Miller et al.
patent: 5729245 (1998-03-01), Gove et al.
patent: 5745088 (1998-04-01), Kornher et al.
Brady III Wade James
Brill Charles A.
Nguyen Chanh
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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