Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-03-17
2001-06-05
Zarabian, A. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185230
Reexamination Certificate
active
06243297
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor storage device, and more specifically, it relates to a write control technology that may be applied in a non-volatile memory which allows an electrical write.
FIG. 2
illustrates a schematic structure of a semiconductor storage device (e.g., an EPROM) in the prior art. In
FIG. 2
, the illustration of circuits such as an address decoder employed to generate a decode signal and a sense amplifier employed to read out stored data is omitted.
This EPROM is provided with a plurality of memory arrays
100
, . . .
10
n
having structures identical to one another.
For instance, the memory array
100
is provided with word lines WL
0
, WL
1
, . . . , WLn positioned parallel to one another and drain lines DL
0
, DL
1
, . . . and source lines SL
0
, SL
1
, . . . positioned perpendicular to the word lines WL
0
WLn. A memory cell
11
is connected at each intersecting point at which one of the word lines WL
0
~WLn and one of the drain lines DL
0
~intersect each other. The memory cell
11
is constituted of a field effect transistor provided with a floating gate which is insulated from other electrodes. The control gate of this field effect transistor is connected to a word line WL, its drain is connected to a drain line DL and its source is connected to a source line SL.
The individual drain lines DL
0
, DL
1
, . . . are connected to a write control line
13
via N-channel MOS transistors (hereafter referred to as “NMOSs”)
120
,
121
. . . respectively. The on/off control of the even-numbered NMOSs
120
, . . . is achieved by an even number selection signal SE
0
, whereas on/off control of the odd-numbered NMOSs
121
, . . . is achieved by an odd number selection signal SO
0
. In addition, the individual source lines SL
0
, SL
1
, . . . are respectively connected to bit lines BL
0
, BL
1
, . . . via NMOSs
140
,
141
, . . . the on/off states of which are controlled by a memory array selection signal SS
0
.
This EPROM is further provided with word line drive circuits
200
,
201
, . . .
20
n
employed to drive the individual word lines WL
0
~WLn respectively, a write control circuit
30
that drives the right control line
13
and data write circuits
401
,
402
, . . . employed to drive the bit lines BL
0
, BL
1
, . . . during a data write.
The word line drive circuits
200
20
n
assume structures that are identical to one another. For instance, the word line drive circuit
200
generates and outputs a selection signal for the word line WL
0
in conformance to a decode signal DEC
0
provided by an address decoder (not shown).
In more detail, when the decode signal DEC
0
is at level “L”, indicating “non-selection,” the word line drive circuit
200
outputs at ground voltage GND to the word line WL
0
. When the decode signal DEC
0
is at level “H” indicating “selection,” on the other hand, the word line drive circuit
200
outputs a voltage as described below to the word line WL
0
in conformance to a program mode signal/PGM (“/” indicates inversion). Namely, the word line drive circuit
200
outputs a program voltage VPP (e.g., 10 V) during a data write, whereas it outputs a source voltage VCC (e.g., 4 V) during a data read.
The write control circuit
30
outputs a control voltage MCD (=6 V) which is calculated as “source voltage VCC+2Vtn (Vth=approximately 1 V: the threshold voltage of the NMOS)” when a reset signal RST at level “L” is input to set the write control circuit
30
in a write operation state, and outputs the ground voltage GND when a reset signal RST at level “H” is input to set it in a reset state.
The individual data write circuits
401
, . . . assume structures that are roughly identical to one another. For instance, the data write circuit
401
outputs the ground voltage GND or the source voltage VCC in conformance to the level of an input data signal DI
1
(either “L” or “H”) when the reset signal RST is at level “L” and a write operation has been specified by the program mode signal/PGM. When a read operation has been specified by the program mode signal/PGM, the output side of the data write circuit
401
enters a high impedance state. In addition, when the reset signal RST is at level “H”, the output side of the data write circuit
401
is connected to the ground voltage GND.
The data write operation performed by the EPROM in the prior art is now explained.
Prior to a write operation, the reset signal RST is set to level “L” and the program mode signal/PGM is set to level “H”. Then, an address signal that specifies the address of a memory array in which data are to be written is provided to an address decoder (not shown). The address decoder outputs a memory array selection signal SS
0
for selecting a specific memory array (e.g., the memory array
100
). Also, the decode signal DEC
0
for selecting one of the word lines (e.g., the word line WL
0
) in the memory array
100
is provided to the word line drive circuit
200
. An input data signal DI
1
(with its level at, for instance, “L”) and an input data signal DI
2
(with its level at, for instance, “H”) constituting the data to be written are respectively provided to the data write circuits
401
and
402
.
The memory array
100
, which has been selected by the memory array selection signal SS
0
, becomes connected to the bit line BL, whereas the memory arrays
101
~
10
n
that have not been selected are disconnected from the bit line BL. In addition, a selection signal at the source voltage VCC (4 V) is commonly applied to the control gates of all the memory cells
11
connected to the selected word line WL
0
by the word line drive circuit
20
. The control voltage MCD at 6 V is applied to the drain of a selected memory cell
11
by the write control circuit
30
, whereas the source becomes connected to the data write circuit
40
via the source line SL and the bit line BL.
Next, the program mode signal/PGM is set to level “L” over a specific length of time, and the data write operation starts. When the program mode signal/PGM is set to level “L”, the selection signal output to the word line WL
0
by the word line drive circuit
200
is set to the program voltage VPP (10 V). In addition, the voltages output by the data write circuits
401
and
402
to the bit lines BL
1
and BL
2
respectively are set to the ground voltage GND and “the source voltage VCC—the threshold voltage Vth” in correspondence to the data that are input.
The program voltage VPP (=10 V) is applied to the control gate of the memory cell
11
that is selected with the address signal and specified to have the input data DI
1
at level “L” written therein, with the control voltage MCD (=6 V) applied to its drain and the ground voltage GND applied to its source. In this memory cell
11
, since a large difference in the potential (10 V) occurs between its control gate and its source and a large difference in the potential (6 V) occurs between its drain and its source, some of the elections flowing between the drain and the source become accelerated to gain energy, and thus they jump the energy barrier constituted of the gate insulating film to be injected into the floating gate.
The program voltage VPP (=10 V) is applied to the control gate of the memory cell
11
that is selected with the address signal and specified to have the input data DI
2
at level “H” written therein, with the control voltage MCD (=6 V) applied to its drain and “the source voltage VCC~the threshold voltage Vth (=3 V)” applied to its source. In this case, since the difference in the potential between the control gate and the source is 7 V and the difference in the potential between the drain and the source is 3 V, the level of the energy of the electrons flowing between the drain and the source is low and, consequently, the electrons are not injected into the floating gate.
When the data write to the word line WL
0
at the memory array
100
specified with the address signal is completed, the program mode signal/PGM is set to level “H” a
OKI Electric Industry Co., Ltd.
Rabin & Champagne, P.C.
Zarabian A.
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