Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1998-12-09
2001-08-07
Malzahn, David H. (Department: 2121)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
06272509
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a filter device used in a modulator or the like in a transmitter.
BACKGROUND OF THE INVENTOION
Recently, in portable telephone, cable television, communication modem, etc., digital modulation is employed, and time division multiple access (hereinafter called TDMA) is widely used in communication control. As the modulator, a filter device is used for limiting the frequency band. In the filter device, a memory is often used for reducing the circuit size.
FIG. 6
shows a conventional filter device using a memory. Input signal data
100
is entered in an n-bit shift register
8
. The output of the shift register
8
is used as a higher address of a memory
5
. A signal generated in an address control circuit
4
is used in a lower address of the memory
5
. The output of the memory
5
is converted into an analog signal by a digital to analog converter (hereinafter called D/A converter)
6
.
Supposing n different impulse response waveforms corresponding to 1 or 0 of the data of each bit position of the shift register
8
to be generated, each bit of the shift register
8
combined with the waveform interference given to a specific bit position j (1≦j≦n) is digitized. The information to be stored in the memory
5
is this digitized data, and it is converted into an analog signal by the D/A converter
6
. The signal generated in an address control circuit
4
used in the lower address of the memory
5
is for over-sampling the analog output signal of the D/A converter
6
for a period of input of next data at time t+1, from the state of the shift register
8
at a certain time t.
When the output of the shift register
8
accesses the memory
5
, the waveform interference of the impulse response waveform of each bit position on the specific bit position j can be issued, and the filter device characteristic can be designed by design of information stored in the memory
5
.
Thus, the filter device can be composed in a circuit constitution using a memory.
FIG. 7
shows other prior art of filter device using a memory. Input signal data
100
is entered in an n-bit shift register
27
. The output of the shift register
27
is used as a higher address of a memory
14
. The signal generated in an address control circuit
18
is used in a lower address of the memory
14
. The output of the memory
14
is converted into an analog signal by a D/A converter
17
.
Each one of n different impulse response waveforms corresponding to 1 or 0 of the data of each bit position of the shift register
27
is digitized by combining with the waveform interference given to a specific bit position (1≦j≦n). The information to be stored in the memory
14
is this digitized data, and it is converted into an analog signal by the D/A converter
17
. The signal generated in an address control circuit
18
used in the lower address of the memory
14
is for over-sampling the analog output signal of the D/A converter
17
for a period of input of next data at time t+1, from the state of the shift register
27
at a certain time t.
By accessing the memory
14
by the output of the shift register
27
, the waveform interference of the impulse response waveform of each bit position on the specific bit position j can be issued, and the filter characteristic can be designed by design of information stored in the memory
14
.
Thus, in the circuit constitution using the memory
14
, the circuit size can be reduced as compared with the circuit using a multiplier.
However, the TDMA is a method of transmission by repeating transmission and stop of output signals of the modulator in a burst manner. Accordingly, in the prior art as shown in
FIG. 6
, the output of the filter device is changed drastically by transmitting or stopping. As a result, numerous large-peak signals are generated in a wide frequency band, and a significant interference is caused on other channels remote in frequency, and many errors are generated. Therefore, in such prior art as shown in
FIG. 6
, the performance as the modulator cannot be guaranteed.
Or, in the case of the filter device as shown in
FIG. 7
, the circuit size is determined by the memory size, that is, the number of stages of the shift register
27
. However, the number of stages of the shift register
27
determines the performance indices of the modulator such as the modulation precision, and it cannot be curtailed extremely. Downsizing of circuit is the most important design element for the filter device. However, in the prior art shown in
FIG. 7
, when the number of stages of the shift register
27
is curtailed, the performance of the modulator such as modulation precision deteriorates, and the performance as the modulator cannot be assured.
The invention is devise d in the light of the above problems, and it is hence an object thereof to remove the defects of the prior arts, and prevent drastic changes of output modulation signal and assure the performance as the modulator if transmission and stop of the output modulation signal are repeated frequently by using the TDMA in the communication control.
It is also an object of the invention to prevent deterioration of performance such as modulation precision and assure the performance as modulator if the circuit size is reduced by curtailing the number of stages of the shift register.
SUMMARY OF THE INVENTION
To achieve the objects, the invention comprises a shift register, a plurality of memories connected to this shift register and increased in the bit width of input address by one bit each, and a selector for selecting outputs from these plurality of memories, in which the shift register output is used as a higher side address of each one of the memories, a lower side address of each one of the memory addresses is common, the bit width of the higher side address increases by one bit each starting from one bit, and addresses are assigned sequentially from the lower side of the higher side address of the memories depending on the shift from the lowest side bit of the shift register.
The data entered in the filter device is put into the shift register. After the beginning data after start of transmission is shifted to the first bit of the shift register, the higher side address width of the memory selects the memory output of one bit. When the second data is put into the shift register and the beginning data is shifted to the second bit, the higher side address width of the memory selects the memory output of two bits. When the next data is put into the shift register and the beginning data is shifted to the third bit, the higher side address width of the memory selects the memory output of three bits. In this manner, the memory of address width corresponding to the bit position of the beginning data being shifted is selected successively.
At the bit position of the shift register corresponding to the higher side address of each memory, the impulse response corresponding to the data at each bit position is considered. Each bit combined with the waveform interference given to the position of a specific bit of the shift register is digitized (for example, if the higher side address width of the memory has three bits, it is considered that there is an impulse response waveform corresponding to the data at each position of the input side three bits of the shift register). The information to be stored in each memory is its digitized data.
The effect of impulse response of data of a certain bit position on the waveform interference given to other bit position becomes larger as coming closer to the bit position for issuing impulse response. By changing over the selection of memory output depending on the bit shift on the shift register of the beginning data, it is possible to control to increase gradually the degree of effect of the impulse response on the specific bit position.
In this way, by changing over the memory output depending on the beginning data position entered in the shift register, it is possible to control to increase gradually the degree of effect
Doi Atsushi
Fuke Tetsuya
Furukawa Hitonobu
Kitamura Hideya
Kitamura Hirokazu
Malzahn David H.
Matsushita Electric - Industrial Co., Ltd.
Rossi & Associates
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