Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-04-21
2001-09-18
Phan, Trong (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185290
Reexamination Certificate
active
06292396
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority from prior French Patent Application No. 99-05051, filed Apr. 21, 1999, the entire disclosure of which is hereby incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to electrical non-volatile memory and more particularly relates to an improved Electrical Erasable Programmable Read Only Memories (EEPROMs) having an electrical erase field which reduces the aging of tunnel oxide.
2. Description of Related Art
The present invention relates to a device for the programming of an electrically erasable programmable read-only or non-volatile memory, especially of the EEPROM or flash EEPROM type.
Electrically programmable non-volatile memories are usually organized in matrices of cells each placed at the intersection of a bit line and a word line. Each cell has a floating-gate MOS transistor. It is this floating gate that enables the storage of the binary information through the capacitance formed by the floating gate and the control gate of the transistor.
Each cell of a memory of this kind is electrically programmable to contain a binary information that is a “1”, the programming operation then being a so-called write operation or a “0”, the programming operation then being an erase operation.
These erase and write operations enable the modification of the charge of a floating gate by an electrical field, so that the threshold voltage of the floating-gate transistor of the cell is modified. It is known in the EEPROM art that the threshold voltage of a transistor is the minimum voltage to be applied between its gate and its source so that it is conductive. This threshold voltage is modified by varying the charge carried by the gate. If the gate carries a quantity of positive charges, the threshold voltage is thereby diminished. If it carries a quantity of negative charges, the threshold voltage is thereby increased.
Depending on the type of programming operation performed, namely whether it is a write operation or a read operation, the charge of the floating gate is made to vary by making a certain current travel in one direction or the other through a thin layer of tunnel oxide located beneath the floating gate, and the semiconductor substrate. Depending on the direction of the current, namely depending on the polarity of the electrical field applied, the floating gate is charged so that a quantity of positive charges is retrieved or it is discharged so that a quantity of negative charges is retrieved for a quantity of zero charges when the cell is in the blank state.
If the cell has been erased, the capacitance associated with the floating gate is negatively charged, and the threshold voltage of the cell is higher than that of a blank cell.
If the cell has been programmed, the capacitance associated with the floating gate is positively charged, and the threshold voltage of the cell is lower than that of a blank cell.
It is know in the EEPROM art that, the successive erase and write operations cause the memory cell to age. More particularly, this aging affects the tunnel oxide of these cells due to the total quantity of charges that flow through the tunnel oxide following the successive erasing and writing cycles.
The aging of the tunnel oxide has several undesirable consequences may be expressed in different ways, namely:
one short coming of the oxide aging is that the tunnel oxide may have leakages so that the cell is no longer capable of preserving a sufficient quantity of charge to represent the binary information programmed, during a guaranteed retention period;
another short coming the tunnel oxide no longer permits the accurate passage of the charges whether in erasure or in writing, so that the cell cannot be reprogrammed;
Now, the quality of a non-volatile memory is measured by the data retention period and by the number of permissible programming cycles. And this quality of non-volatile memories is directly related to the aging of the tunnel oxide.
To limit the aging of the tunnel oxide, it is necessary to reduce the quantity of charges stored in the cells. Diminishing the quantity of stored charges means diminishing the gaps between the threshold voltages corresponding to the blank, written and erased states.
To enable a reduction in the quantity of charges stored in the cells, it is necessary to be able to use the most sensitive possible read circuitry that can discriminate between two logic states “0” and “1” close to the blank state. Circuits of this kind exist, based on current/voltage converters that are well known and used by those skilled in the art.
However, to reduce the aging of the tunnel oxide, it is also necessary to have a programming device capable of generating programming signals suited to the production of this very small quantity of charges in the cells.
The quantity of charges in the memory cells is a function of the programming time. This programming time is specified for each memory. In practice, there are known ways of controlling this parameter of the programming, in a very stable manner, through a time lag circuitry. This programming time therefore in no way increases the aging of the tunnel oxide.
The quantity of charges in memory cells is also a function of the voltages applied to the cells, and more specifically of the programming voltage. It will be shown that this parameter of the programming itself affects the aging of the tunnel oxide of the memory cells.
Indeed, for one and the same programming voltage VPP used in erasure or writing, the quantity of charges induced is not the same (in terms of absolute value) in one direction or the other, the electrical field applied not having the same intensity (in terms of absolute value).
Let us take the example of a cell of an EEPROM type memory organized according to a matrix of bit lines and word lines. A cell of this kind is represented schematically in FIG.
1
. In a well-known way it includes a selection transistor Ts whose gate g
s
is connected to a word line W
1
of the memory and whose drain d
s
is connected to a bit line B
1
of the memory. It furthermore comprises a floating-gate transistor Tm containing the binary information programmed in the cell. This floating-gate transistor comprises a control gate g
c
and a floating gate g
f
. Its drain d
m
is connected to the source s
s
of the selection transistor. The word line W
1
, the bit line B
1
, the control gate g
c
and the source s
m
of the floating-gate transistor receive control voltages respectively referenced V
W1
, V
B1
, V
gc
and V
sm
, given by a circuitry for the selection of the memory cells (not shown).
V
gf
refers to the potential on the floating gate and V
dm
the potential of the drain on the floating-gate transistor Tm.
To program a cell, a programming voltage commonly referenced VPP is used. This voltage is applied appropriately to create the required electrical field, for a write or erase operation. This programming voltage is usually produced internally in the integrated circuit containing the memory, by a circuit for the generation of a high voltage from the logic supply voltage Vcc of the integrated circuit. This generation circuit usually comprises a charge pump with an oscillator to produce the necessary clock signals. An example of such a circuit is described in detail in the U.S. non-provisional patent application Ser. No. 08/128,871 filed Sep. 29, 1993 entitled “VOLTAGE BOOSTER CIRCUIT OF THE CHARGE-PUMP TYPE WITH A BOOTSTRAPPED OSCILLATOR”, now [pending], which is incorporated herein by reference.
In a practical example, where the logic supply voltage Vcc equals 5 volts, the programming voltage generated internally may be equal to about 16 volts. This high programming voltage is applied to the cells differently, depending on the type of programming to be carried out.
FIG. 2
a
gives a schematic view of what happens during an erasure type of programming operation. The voltage V
gc
applied to the control gate is equal to the programming voltage
Fleit Kain Gibbons Gutman & Bongini P.L.
Galanthay Theodore E.
Gibbons Jon A.
Phan Trong
STMicroelectronics S.A.
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