Reexamination Certificate
1999-02-02
2001-07-31
Pham, Long (Department: 2823)
C257S408000
Reexamination Certificate
active
06267479
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having a high withstanding voltage transistor and a low withstanding voltage transistor provided in a single chip and a method for manufacturing the same.
2. Description of the Background Art
FIG. 57
is a cross-sectional view showing a former semiconductor device
10
having a high withstanding voltage transistor and a low withstanding voltage transistor provided in a single chip. The semiconductor device
10
comprises N-channel MOS (NMOS) transistors
12
and
14
and P-channel MOS (PMOS) transistors
16
and
18
. The NMOS transistor
12
and the PMOS transistor
16
are low withstanding voltage transistors which are driven at a given low voltage (e.g., 1.8 volts). In contrast, the NMOS transistor
14
and the PMOS transistor
18
are high withstanding voltage transistors which are driven at a given high voltage (e.g., 3.3 volts).
The NMOS
12
and the PMOS driven at the low operating voltage (which are called “low voltage MOS transistor” hereunder) are used for a portion of circuitry which exchanges signals solely within the semiconductor device
10
, such as a logic circuit. The low voltage MOS transistors
12
and
14
have thin-film gate oxide films
20
and
22
respectively. In contrast, the NMOS
14
and the PMOS
18
driven at the high operating voltage (which are called “high voltage MOS transistor” hereunder) are used for a portion of the interface between the semiconductor device
10
and an external circuit. The high voltage MOS transistors
14
and
16
have thick-film gate oxide films
24
and
26
respectively.
A p-type channel region
28
is formed below the NMOS transistor
12
, and a p-type channel region
30
is formed below the NMOS transistor
14
. N-type lightly doped drain extensions (LDDEX)
32
and n-type source/drain (S/D) regions
36
are formed on each side of the channel region
28
, and n-type LDDEX regions
34
and n-type source/drain regions
38
are formed on each side of the channel region
30
. The LDDEX regions
32
and
34
are formed so as to be lower in impurity concentration than the source/drain regions
36
and
38
.
An n-type channel region
40
is formed below the PMOS transistor
16
, and an n-type channel region
42
is formed below the PMOS transistor
18
. P-type LDDEX regions
44
and p-type source/drain regions
48
are formed on each side of the channel region
40
, and p-type LDDEX regions
46
and p-type source/drain regions
50
are formed on each side of the channel region
42
. The LDDEX regions
44
and
46
are formed so as to be lower in impurity concentration than the source/drain regions
48
and
50
.
In
FIG. 57
, reference symbol PA-A represents a depthwise impurity profile of the channel region
28
taken along line A—A; PB-B represents a depthwise impurity profile of the channel region
30
taken along line B—B; PC-C represents a depthwise impurity profile of the channel region
40
taken along line C—C; and PD-D represents a depthwise impurity profile of the channel region
42
taken along line D—D. Furthermore, in
FIG. 57
, reference symbol Pa represents an impurity profile of the LDDEX region
32
; Pb represents an impurity profile of the LDDEX region
34
; Pc represents an impurity profile of the LDDEX region
44
; and Pd represents an impurity profile of the LDDEX region
46
. As shown in
FIG. 57
, in the former semiconductor device
10
, the transistors of the same conductivity type have different impurity profiles in the channel regions(i.e., PA-A≢PB-B and PC-C≢PD-D) while having identical impurity profiles in the LDDEX regions(i.e., Pa=Pb, and Pc=Pd).
In the semiconductor device
10
, an appropriate threshold voltage must be assigned to the low voltage MOS transistors
12
and
16
as well as an another appropriate threshold voltage must be imparted to the high voltage MOS transistors
14
and
18
. As mentioned above, in the former semiconductor device
10
, the channel regions
28
and
40
of the low voltage MOS transistors
12
and
16
are given impurity profiles different from that of the channel regions
30
and
42
of the high voltage MOS transistors, whereby the threshold voltage required by each transistor is realized.
A method of manufacturing the conventional semiconductor device
10
will now be described by reference to
FIGS. 58 through 63
.
FIG. 58
is a cross-sectional view showing a substrate
52
of the semiconductor device
10
. In
FIG. 58
, an isolation oxide film
53
is formed on the substrate
52
in order to separate from one another active regions in which transistors are to be formed. The four active regions shown in
FIG. 58
are subjected to the following processing, so that the NMOS transistor
12
, the NMOS transistor
14
, the PMOS transistor
16
, and the PMOS transistor
18
are formed in the order from the left side of the drawing. These active regions will be hereinafter referred to respectively as a “low voltage NMOS region
54
,” a “high voltage NMOS region
56
,” a “low voltage PMOS region
58
,” and a “high voltage NMOS region
60
.”
FIGS. 59A
to
59
D are cross-sectional views for describing formation of N-type semiconductor islands (N-type islands)
62
and
64
in the respective PMOS regions
58
and
60
on the substrate
52
. As shown in
FIGS. 59A and 59B
, during the process of forming the N-type islands
62
and
64
, “P” ions and “As” ions are implanted into both of the PMOS regions
58
and
60
under identical conditions. Subsequently, as shown in
FIGS. 59C and 59D
, “As” ions are implanted into each of the PMOS regions
58
and
60
in a phased manner under differing conditions. As a result of the foregoing processing operations, two N-type islands
62
and
64
having different impurity profiles are formed on the substrate
52
.
FIGS. 60A
to
60
D are cross-sectional views for describing formation of P-type semiconductor islands (P-type islands)
66
and
68
in the respective NMOS regions
54
and
56
on the substrate
52
. As shown in
FIGS. 60A and 60B
, during the process of forming the P-type islands
66
and
68
, “B” ions are implanted into both of the NMOS regions
54
and
56
under identical conditions.
Subsequently, as shown in
FIGS. 60C and 60D
, “B” ions are implanted into each of the NMOS regions
54
and
56
in a phased manner under differing conditions. As a result of ion implantation, two P-type islands
66
and
68
having different impurity profiles are formed on the substrate
52
.
FIGS. 61A
to
61
C are cross-sectional views for describing formation of lightly-doped drain (LDD) sections in the respective islands
62
,
64
,
66
, and
68
. As shown in
FIG. 61A
, during the process of forming an LDD region, thin-film oxide films
70
and
74
are formed on the surface of the low voltage NMOS regions
54
and the low voltage PMOS region
58
respectively.
Further, a thick-film oxide films
72
and
76
are formed on the surface of the high voltage NMOS region
56
and the high voltage PMOS region
60
. Each of the oxide films
70
to
76
are provided with a gate electrode
78
.
As shown in
FIG. 61B
, during the process of forming an LDD region, “As” ions are implanted into the low voltage NMOS region
54
from above the oxide film
70
, as well as into the high voltage NMOS region
56
from above the oxide film
72
, under identical conditions. As a result of implantation of “As” ions, a channel region
28
, which has an impurity profile identical to that of the island
66
, is formed below the gate electrode
78
of the NMOS region
54
, and a channel region
30
, which has an impurity profile identical to that of the island
68
, is formed below the gate electrode
78
of the NMOS region
56
. Further, LDD sections
80
and
82
having a comparatively lower impurity concentration are formed on each side of the channel region
28
and
30
respectively.
As shown in
FIG. 61C
, during the pr
Higashitani Keiichi
Kawashima Hiroshi
Yamada Keiichi
Coleman William David
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Pham Long
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