Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Field effect transistor
Reexamination Certificate
1999-06-30
2001-08-21
Jackson, Jr., Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Field effect transistor
C257S627000, C257S192000
Reexamination Certificate
active
06278141
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to semiconductor devices and more particularly to a compound semiconductor device operating in an enhancement-mode.
Compound semiconductor devices have an advantageous feature of high operational speed due to the small effective mass of electrons. Further, in view of low operational voltage, compound semiconductor devices are used extensively in electronic apparatuses for use in ultra-high frequency applications including mobile telephones and portable telephones. Conventionally, depletion-mode compound semiconductor devices have been used successfully in such ultra-high frequency applications for the final stage power transistor.
On the other hand, the use of such a depletion-mode power transistor has caused the problem that a negative voltage source has to be provided in the electronic apparatus in addition to a positive voltage source for driving the depletion-mode power transistor. In relation to the use of the additional voltage source, it has been difficult, in conventional electronic apparatuses having a depletion-mode compound semiconductor device as a power transistor, to reduce the size and cost or power consumption.
Meanwhile, compound semiconductor devices of the enhancement-mode have an advantageous feature in that the negative voltage source is not necessary. Thereby, the enhancement-mode compound semiconductor devices are promising devices for reducing the size and cost or power consumption of the electronic apparatus.
When using an enhancement-mode compound semiconductor device in such ultra-high frequency applications, it is desired to reduce the leakage current in the turn-off state thereof and increase the current density in the turn-on state as much as possible, so that high output power and high efficiency are achieved.
In an enhancement-mode power FET, on the other hand, the turn-off state leakage current and the turn-on state current density are generally in a trade-off relationship, and it has been difficult to increase the turn-on state current density and simultaneously minimize the turn-off state leakage current.
FIG. 1
shows the construction of a typical enhancement-mode MESFET
10
having a diffusion region.
Referring to
FIG. 1
, the MESFET
10
is formed on a semi-insulating GaAs substrate
11
and includes a GaAs channel layer
12
of the n-type formed on the substrate
11
, wherein a gate electrode
13
A is formed on the channel layer
12
in correspondence to a channel region CH defined in the channel layer
12
. Further, the channel layer
12
is formed with diffusion regions
12
A and
12
B of the n-type at respective lateral sides of the gate electrode
13
A, such that the diffusion regions
12
A and
12
B reach the GaAs substrate
11
. Further, ohmic electrodes
13
B and
13
C are formed on the diffusion regions
12
A and
12
B respectively, and a passivation film
14
is provided on the channel layer
12
so as to cover the gate electrode
13
A and the ohmic electrodes
13
B and
13
C.
In the enhancement-mode MESFET
10
of
FIG. 1
, it is necessary to increase the threshold voltage V
th
in order to reduce the leakage current in the turn-off state, wherein the threshold voltage V
th
is represented, in the injection type MESFET of
FIG. 1
, as
V
th
=V
bi
−qN
d
a
2
/2&egr;,
wherein N
d
and a represent respectively the impurity concentration level and the thickness of the channel layer
12
.
From the equation above, it is understood the impurity concentration level N
d
or the thickness a of the channel layer
12
has to be reduced when to increase the magnitude of the threshold voltage V
th
.
On the other hand, the characteristic curve of
FIG. 2
indicates that the drain current I
ds
is reduced also when the impurity concentration level N
d
or the thickness a of the channel layer
12
is reduced. It should be noted that
FIG. 2
represents the relationship between the drain current I
ds
and the gate voltage V
gs
. In other words, the relationship of
FIG. 2
indicates that the maximum current density in the turn-on state of the MESFET
10
is reduced inevitably when the impurity concentration level N
d
in the channel layer
12
is reduced or the thickness a of the channel layer
12
is reduced for suppressing the turn-off state leakage current.
On the other hand, it has been known that the threshold voltage V
th
of a compound semiconductor device such as a MESFET is affected by the orientation of the gate electrode. Reference should be made, for example, to the Japanese Laid-Open Patent Publication 64-000770 or to the Japanese Laid-Open Patent Publication 57-135681. In relation to such a shift of the threshold voltage V
th
, caused by the setting of the gate electrode orientation on the compound semiconductor substrate, there is a stress analysis presented by Onodera (Onodera, T. et al., IEEE ED vol. 36, no. 9, pp. 1580-1590), concluding that such a change of the threshold voltage V
th
is caused as a result of the piezoelectric charges induced in the channel layer
12
in correspondence to the part right underneath the gate electrode
13
A as represented in FIG.
3
.
FIG. 4
represents the definition of the crystal orientation used in the present invention.
Referring to
FIG. 4
, an etch pit is formed on a (100)-oriented surface of a GaAs crystal by a wet etching process, wherein it can be seen that the crystal orientation [01{overscore (1)}] and the crystal orientation [011] are defined on the (100) surface based on the orientation of the ordinary mesa structure and the inverse mesa structure formed as a result of the wet etching process.
FIG. 5
shows the relationship between the gate length L
g
and the threshold voltage V
th
for the case in which the gate electrode
13
A is formed in the [011] direction and also for the case in which the gate electrode
13
A is formed in the [01{overscore (1)}] direction. The result of
FIG. 5
assumes that the GaAs substrate
11
has a (100) principal surface.
Referring to
FIG. 5
, it can be seen that the threshold voltage V
th
decreases sharply with the gate length L
g
when the gate electrode
13
A is formed in the [011] orientation. In this case, the threshold voltage V
th
drops conspicuously when the gate length L
g
has been reduced below 5 &mgr;m. Thereby, the operational mode of the MESFET changes to the depletion mode. On the other hand, in the case the gate electrode
13
A is formed in the [01{overscore (1)}] orientation, it can be seen that the threshold voltage V
th
remains more or less constant even in such a case in which the gate length L
g
is reduced below 5 &mgr;m.
The result of
FIG. 5
indicates that the MESFET
10
continues to operate in the enhancement-mode even in the case the gate length L
g
is reduced below 5 &mgr;m, as long as the gate electrode
13
A is formed in the [01{overscore (1)}] orientation.
On the other hand, the characteristic curve of
FIG. 6
indicates that the drain current I
ds
is reduced, when the gate electrode
13
A is formed in the [01{overscore (1)}] orientation. Apparently, this is due to the effect of the piezoelectric charges induced in the channel layer
12
in correspondence to the channel region CH right underneath the gate electrode
13
A. It should be noted that
FIG. 6
is a diagram similar to FIG.
2
and shows the relationship between the drain current I
ds
and the gate voltage V
gs
.
Further, in view of the fact that the gate turn-on voltage has a constant value of about 0.8 V in the construction of
FIG. 1
, in which the gate electrode
13
A makes a direct Schottky contact with the channel layer
12
, it has been difficult to construct an enhancement-mode MESFET having a threshold voltage V
th
exceeding 0.3 V, even if the gate electrode is formed with the [01{overscore (1)}] orientation. It should be noted that the foregoing constant gate turn-on voltage of about 0.8 V is determined by the Schottky barrier height formed between the gate electrode
13
A an
Mitani Eizo
Oguri Hiroyuki
Armstrong Westerman Hattori McLeland & Naughton LLP
Fujitsu Limited
Jackson, Jr. Jerome
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