Integrating analog to digital converter with improved...

Details Integrating analog to digital converter with improved... Integrating analog to digital converter with improved...

1999-04-13

2001-06-05

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S155000

Reexamination Certificate

active

06243034

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to the art of analog-to-digital (A/D) converters, and more particularly, to integrating A/D converters.
DESCRIPTION OF THE RELATED ART
Analog-to-digital converters (ADCs) are circuits used to convert signals from the analog domain, where the signals are represented by continuous quantities such as voltage and current, to the digital domain. These circuits can be implemented in a large number of ways. Established A/D conversion techniques include flash, sigma-delta, sub-ranging, successive approximation, and integrating.
Integrating ADCs function by integrating or averaging the input signal over a fixed time. This operates to reduce noise and eliminate interfering signals. Integrating ADCs are thus often used for digitizing signals that are not changing rapidly with time, such as DC signals, or in applications where the desired result is a time average of the input signal. Integrating ADCs are used in applications where a very high resolution is required at a comparatively low sample rate.
A traditional integrating ADC is illustrated in FIG.
1
. As shown, the integrating ADC in
FIG. 1
comprises an integrator, a comparator, and control logic. The integrating ADC converts an unknown analog input voltage Vin into a digital signal, known in the art as an “integrator count.”
As shown in
FIG. 1
, the analog input voltage Vin is provided through a switch SW
1
to an input of the integrator
402
. The integrator
402
comprises an operational amplifier (op-amp)
404
and a parallel capacitor C
1
. The integrator
402
receives the unknown analog input voltage Vin and provides an integrator output voltage Vint to a comparator
408
. The comparator
408
compares Vint with a reference voltage, e.g., ground, and produces a comparator output voltage Vc. The comparator output Vc is a digital signal which indicates whether Vint was greater or lesser than the reference voltage.
The comparator
408
provides the output Vc to the control logic
410
, which in turn controls the switch SW
1
. The switch SW
1
is controlled to selectively couple either the input voltage Vin or a reference voltage Vref to an input of the integrator at any given time. When the input voltage Vin is coupled to the integrator
402
, the integrator
402
charges. When the reference voltage Vref is coupled to the integrator
402
, the reference voltage Vref operates to discharge the integrator
402
. The reference voltage Vref may either be positive or negative and may be either a voltage or current source. The control logic
410
outputs the slope count or integrator count.
FIG. 2
illustrates a technique known as dual slope integration which has been employed by traditional integrating ADCs, as shown in
FIG. 1
, in order to generate a digital output. The dual slope approach is a commonly used integrating A/D architecture. The dual slope method uses two half cycles, referred to as the up slope, run-up interval, or ramp-up interval (RU) and the down slope, run-down interval, or ramp-down interval (RD).
In the dual slope integrating ADC, the unknown input analog voltage, Vin, is applied to the integrator
402
for a ramp-up (RU) interval of duration T as depicted in FIG.
2
. The control logic
410
then adjusts the switch SW
1
to couple the reference voltage Vref to the input of the integrator. As a result, the analog input voltage Vin is disconnected and simultaneously the reference discharging voltage Vref is applied to the integrator
402
during a ramp-down (RD) interval for a duration t. When the capacitor C
1
becomes completely discharged, the RD interval ends and hence the integrator output, Vint, is zero. Thus the input signal is integrated during the up slope for a fixed time, and then a reference of opposite sign is integrated during the down slope to return the integrator output to zero.
The duration of the ramp-down time t in the RD interval is typically measured by counting (usually synchronously with a clock) during the RD interval. The value of the unknown analog input voltage Vin is then computed as follows:
V
in=
V
m/
T
Thus the input voltage Vin can be calculated from the integrated voltage Vm divided by the ramp-up time period T, hence essentially computing the average value of Vin for the ramp-up time period T. The integrated voltage Vm can be computed as:
V
m=
V
ref x t
Thus the Voltage Vin can be calculated as:
V
in=t x (
V
ref/
T
)
For a given count or ramp-down time period t, the sensitivity of the ADC increases with a decrease in the rate at which the capacitor C
1
discharges. Therefore, sensitivity may be increased by decreasing the magnitude of Vref. However, a decrease in the magnitude of Vref results in a slower response of the circuit.
The sensitivity of the A/D can also be increased by increasing the maximum voltage, Vm, of the integrator output voltage, Vint, during the RU interval. Vm can be increased by lowering the value of the input resistance prior to the integrator
402
. However, the integrator output voltage, Vint, must be within the bounds of the op-amp 404 power supply voltage limits.
In the dual slope method, the RU or up-slope integration time T can be set to an integer number of periods of the clock. However, the time period t required to return the integrator output to zero will generally not be an exact integer number of clock periods, since Vm can assume any value. Thus there will be a possible error of plus or minus (+/−) 1 count in how well the number of counts in the time period t describes Vin.
One way to improve the resolution of a dual slope integrating A/D converter is to increase the fixed number of clock periods in the RU or up slope, which has the effect of linearly increasing the time required for both the up slope and the down slope. Another way to improve the resolution of a dual slope integrating A/D converter is to lower the reference voltage Vref, so that the RU or up slope time is constant but the down slope time is increased linearly. In either case, the increased resolution requires a linear increase in the number of clock periods in the conversion. Thus the increased resolution comes at the direct expense of conversion time.
Another technique to increase the speed of the dual-slope integrating ADC is to use a pair of resistors, one for ramp-up and the other for ramp-down. The ramp-down resistor has a much greater resistance value than the ramp-up resistor. Thus the ramp-up time is shortened, while the ramp-down time and hence the resolution remains the same. The cost of this technique is an additional resistor and sensitivity of the ADC to the ratio of the two resistors.
A better method for improving the resolution of an integrating A/D converter with a lesser impact on conversion time is to use a multi-slope architecture. The “multisloping” technique maintains high sensitivity and, at the same time, increases the response time of the integrating ADC. U.S. Pat. No. 4,356,600 to Ressmeyer, which is incorporated herein by reference, describes the use of multisloping for producing a digital representative of the unknown analog input voltage, Vin.
A block diagram of a first type of multislope ADC is shown in FIG.
3
. The multislope ADC shown in
FIG. 3
utilizes multislope ramp-down to reduce the time required to perform ramp-down. This multislope ADC differs from the dual slope approach in that there are separate up and down integration resistors, and furthermore, there are multiple values for the down slope integration resistors. Using different resistors for the up and down slope portions introduces the possibility of errors due to resistor mismatch. The dual slope is immune to this problem since only one resistor is used. However, high-quality resistor networks with good temperature tracking and linearity can overcome this disadvantage.
The advantage of the multislope architecture is a decrease in conversion time or an increase in resolution. As shown in
FIG. 4
, the time required for the down slope at a given resolution can be reduced by operating multiple “down” slo

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