Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Reexamination Certificate
1993-09-13
2001-03-27
Sherry, Michael J. (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
C361S111000
Reexamination Certificate
active
06208493
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention generally relates to integrated circuits and, more particularly, to a method and system for protecting integrated circuits against a variety of electrical transients.
BACKGROUND OF THE INVENTION
Integrated circuits are used in a variety of environments including harsh ones that can seriously deter the integrated circuit's proper operation. In general, the phenomena known as electrostatic discharge (ESD) and electrical overstress (EOS) can affect and, in some cases, prohibit the functioning of integrated circuits. ESD may be thought of as high-energy pulse that occurs whenever someone or something carrying an electrical charge touches the integrated circuit. In EOS, a voltage spike of a longer duration exists. An example of EOS occurs when a system is improperly tested or during improper operation of an electrical system that causes a large voltage spike to enter the integrated circuit. In some even harsher environments, such as that of an automobile, a phenomenon known as “load dump” may occur. An example of the load dump electrical transient happens when a battery cable disconnects from the battery terminal as a result of the car hitting a bump or experiencing some other jolt. The disconnected battery cable, if connected to the alternator, may contact a component such as an engine control circuit that has an embedded integrated circuit. This battery cable contact dumps the energy from the alternator into the integrated circuit and can destroy its proper operation.
Integrated circuits that protect against ESD often use on-chip protection at the input and output pins. Protection devices that protect against ESD may protect against high-energy pulses of up to 15 killivolts. On-chip protection device designs for pulses having magnitudes beyond this level are not possible due to practical limits of size on the integrated circuit chip. Circuits that address the EOS and load dump situations may use a metal oxide veristor (MOV) device to absorb the high-energy pulse. MOV devices, however, are bulky and expensive to implement for all integrated circuits that may require protection. The heat that the known protection devices produces also impairs performance of integrate circuits as the temperature rises in the associated silicon substrate region.
SUMMARY OF THE INVENTION
A need, therefore, exists for a method and system that protect integrated circuits against electrical transients such as the ESD, EOS, and load dump transients.
A further need exists for a method and system that protect integrated circuits against electrical transients that consume little of the valuable integrated circuit board space and that cost less than known approaches to implement for various types of electrical transients.
Yet a further need appears for a method and system that in one embodiment protects integrated circuits against not just one type, but a variety of electrical transients, including ESD, EOS, and load dump situations. That is, the needed method and system should have sufficient flexibility to cover a large range of voltage values that may occur during these transients.
The present invention, accordingly, provides a method and system for protecting integrated circuits against electrical transients and overcomes or reduces disadvantages and limitations associated with prior integrated circuit electrical transient protection systems and methods.
One aspect of the invention is a pulse protection device for protecting an integrated circuit from electrical transients. The protected integrated circuit has an integrated circuit substrate region. The pulse protection device includes a protection circuit substrate region that is separate from the integrated circuit substrate region. The integrated circuit substrate region, while different from the protected circuit substrate region may, or may not, be on the same chip. On the protection circuit substrate region is a primary protection circuit that has at least one connection with the integrated circuit for receiving and dissipating the high-energy pulse. Since the protection circuit receives the high-energy pulse protection, instead of the integrated circuit, the integrated circuit is protected against a variety of electrical transients. In the present embodiment, a triggering circuit associates with the integrated circuit and triggers upon the high-energy pulse entering the integrated circuit substrate region. This causes the high-energy pulse to flow to the protection circuit. The protection circuit then shunts the high-energy pulse to ground.
A technical advantage of the present invention is that it provides a compact, effective, and inexpensive solution to protecting integrated circuits against electrical transients. The system of the present invention provides on a separate protection circuit substrate region that may occupy a separate chip or a separate region of the same chip as the chip that the integrated circuit uses. Because the present invention uses a separate chip or separate substrate region, clamping devices like those of known protection schemes need not consume valuable substrate space of the integrated circuit chip or substrate region.
Another technical advantage of the present invention is that it has sufficient flexibility for use in protecting the integrated circuit against a wide variety of electrical transients, including ESD, EOS, and, in some instances, load dump. Also, the protection circuits formed according to the present invention may take a multitude of designs. For example, a protection circuit may have extremely high voltage and relatively lower voltage spike absorbing portions and connections to the integrated circuit so that only those integrated circuit portions that are likely to experience load dump or EOS connect to the higher voltage absorbing portions. The other integrated circuit components may then connect to the relatively lower voltage spike absorbing portions to protect against ESD.
Yet another technical advantage of the present invention is that it removes from the integrated circuit substrate the heat that the protection circuitry generates while protecting the integrated circuit. This insures proper operation of the integrated circuit during and after an electrical transient.
A further technical advantage of the present invention is that the protection circuitry on the protection circuitry substrate may include a variety of components for uniform power dissipation such as a semiconductor rectifier (SCR) or a gate-coupled MOSFET (GCM), depending on the type of electrical transients against which the protection circuitry protects.
In the case of EOS, the use of large devices with uniform power dissipation can improve reliability and reduce yield loss. The present invention allows the desired sizing of the protection circuit to achieve this.
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patent: 4920405 (1990-04-01), Itoh et al.
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patent: 5021853 (1991-06-01), Mistry
patent: 5268588 (1993-12-01), Marum
patent: 314 465 A3 (1989-03-01), None
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Brady W. James
Garner Jacqueline J.
Sherry Michael J.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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