Semiconductor memory device having a plurality of transfer...

Details Semiconductor memory device having a plurality of transfer... Semiconductor memory device having a plurality of transfer...

1996-09-20

2001-03-06

Gossage, Glenn (Department: 2759)

Static information storage and retrieval

Addressing

Sync/clocking

C365S230060

Reexamination Certificate

active

06198687

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a method of accessing a dynamic Random Access Memory (dRAM) in which dynamic memory cells for individual cell access are integrated, and a dRAM system.
2. Description of the Related Art
A conventional semiconductor memory device is generally operated in response to a control signal from an external Central Processing Unit (CPU). In the dRAM, an upper address designation signal, a lower address designation signal, row address strobe {overscore (RAS)}, column address strobe {overscore (CAS)}, write trigger signal {overscore (WE)}, and the like are used. These control signals must be input from the external CPU or the like at a voltage, an order, and a timing which are prescribed by specifications of the semiconductor memory device so as to properly operate the semiconductor memory device.
The row address strobe (to be referred to as an {overscore (RAS)} hereinafter) is a signal for selecting a mode which designates a row of the semiconductor memory device, and a column address strobe (to be referred to as a {overscore (CAS)} hereinafter) is a signal for selecting a mode which designates a column of the semiconductor memory device. In both the read and write modes, signals {overscore (RAS)} and {overscore (CAS)} are always input in the order named.
SUMMARY OF THE INVENTION
A method of accessing a dRAM according to the present invention is characterized in that in a dRAM of an address multiplex system, the order of input of column and row addresses during a read cycle differs from that during a write cycle.
A dRAM system of the address multiplex type according to the present invention is characterized by comprising an address data selector for dividing the row and column addresses from a CPU into upper and lower addresses and time-divisionally supplying them to a dRAM chip, and a gate circuit for designating to the selector which of the upper and lower addresses is to be input first, in response to an external control signal.
According to the method of accessing the dRAM of the present invention, e.g., an arrangement in which a latch-type memory cell is arranged between a bit line and an input/output line is utilized. Thus, during a read cycle, {overscore (RAS)} goes from “1” to “0” prior to {overscore (CAS)}. During a write cycle, on the other hand, {overscore (CAS)} goes from “1” to “0” prior to {overscore (RAS)}. Therefore, no limitation is imposed on the timings of enabling the word line and CSL (column select line) in the write mode, thus ensuring a high-speed write operation of the dRAM and an easy designing thereof.


REFERENCES:
patent: 4758987 (1988-07-01), Sakui
patent: 4811299 (1989-03-01), Miyazawa et al.
patent: 61-142592 (1986-06-01), None

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