Low operational power, low leakage power D-type flip-flop

Details Low operational power, low leakage power D-type flip-flop Low operational power, low leakage power D-type flip-flop

2000-09-05

2001-08-14

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S202000, C327S203000

Reexamination Certificate

active

06275083

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to digital electronic circuits and, in particular, to a flip-flop that has low operational power consumption and low leakage power consumption and that additionally has a sleep mode. In the sleep mode, the output of the flip-flop is held in a state that sets a digital electronic circuit that includes the flip-flop to a low leakage power consumption state.
BACKGROUND OF THE INVENTION
Flip-Flops are the basic storage elements used in synchronous digital VLSI circuits and in other digital electronic circuits. Existing flip-flop designs include the following:
1. Sense-Amp Flip-Flop
2. StrongArm™ 110 Flip-Flop
3. Modified C
2
MOS Flip-Flop
4. Semi Dynamic (SD) Flip-Flop
5. Hybrid Latch (HL) Flip-Flop
6. Pulse Triggered True single-phase clocking Flip-Flop (PTTFF)
7. DSTC Master-Slave Latch
8. 8 transistor D Flip-Flop
9. 9 transistor D Flip-Flop
10. High Speed D Flip-Flop
11. Push Pull Flip-Flop
12. Texas Instruments™ (TI) Low Power Flip-Flop
13. PowerPC™ 603 Flip-Flop
14. Conventional Flip-Flop
15. True Single Phase Clocking (TSPC) Flip-Flop
16. Low Power Flip-Flop
Flip-flop designs 1 through 5, 7 and 13 are described by V. Stojanovic and V. Oklobdzija in Comparative Analysis of Master-Slave Latches and Flip-Flops for High-Performance and Low-Power Systems, 34 IEEE J. S
OLID
-S
TATE
C
IRCUITS
, 536-548 (1999 April). Flip-flop designs 6, 8 and 9 are described by J. Wang, P. Yang and D. Sheng in Design of a 3V 300MHz Low-Power 8-b×8-b Pipelined Multiplier Using Pulse-Triggered TSPC Flip-Flops, 35 IEEE J. S
OLID
S
TATE
C
IRCUITS
(2000 April). Flip-flop design 10 is disclosed in U.S. Pat. No. 6,060,927, entitled High Speed D Flip-Flop, of Lee et al. Flip-flop designs 11 and 16 are described by U. Ko and P. Balsara in High-Performance Energy-Efficient D Flip-Flop Circuits, 8 IEEE T
RANS. ON
VLSI, 94-97 (2000 February). Flip-flop design 13 is disclosed in U.S. Pat. No. 5,789,956, entitled Low Power Flip-Flop, of Mahant-Shetti et al. Flip-flop designs 14 and 15 are described by S. Hsu and S. Lu in A Novel High-Performance Low-Power CMOS Master-Slave Flip-Flop, IEEE Intl. ASIC C
ONF
., 340-343 (1999 September).
Power dissipation has become a major design concern in VLSI circuits for use in portable and battery-powered devices. Flip-flops are an integral component of digital circuits used for data storage. Hence, there is an important need for a flip-flop that not only has low operating power consumption but also has low leakage power consumption when the flip-flop is in a stand-by or sleep mode.
Moreover, as device geometries become smaller, the leakage power consumption increases in proportion to the operating power consumption.
Hence both operating power consumption and leakage power consumption must both be reduced to reduce the overall power consumption. Leakage power consumption is a major concern in portable electronic devices that may operate in a sleep mode for a considerable amount of time. Although many of the flip-flop designs referred to above have low operating power consumption, none of them is optimized to reduce overall power consumption.
Examples of the above-mentioned lack of optimization for overall power consumption in flip-flop designs 1-16 include:
Flip-flop designs 1-10 clock in the D-input every clock cycle (assuming single rising-edge transitions only), regardless of whether the state of the D-input is constant and regardless of whether or not the portion of the circuit that includes the flip-flop is in use. These characteristics lead to unnecessary transitions in the flip-flop and, hence, increased power consumption.
Flip-flop designs 11-16 can be operated in conjunction with clock-gating circuits that control the clock input into the flip-flop. However, operating any of these flip-flop designs in conjunction with a clock-gating circuit results in the potential drawbacks of increased delay times, setup times and hold times. These increased times are due to the dependence of the signal fed to the clock input of the flip-flop on the clock-gating control signal in addition to the normal clock signal. Operating flip-flop designs 11-16 in conjunction with a clock-gating circuit can prevent data from being clocked in on every clock cycle. Thus, operating the flip-flop with a clock gating circuit suffers from the shortcoming that a clock dependency persists as a result of controlling the gating of the data. Moreover, the clock-gating circuitry adds additional area and increases timing complexity.
In Estimation of Standby Leakage Power in CMOS Circuits Considering Accurate Modeling of Transistors Stacks, PROC. IEEE & ACM I
NTL
. S
YMP. ON
L
OW
P
OWER
E
LECTRONICS
& D
ESIGN
, 239-244 (1998 August), Z. Chen, M. Johnson, L. Wei and K. Roy disclose applying a suitable input vector to circuitry to effect a substantial reduction in leakage power consumption of the circuitry. However, none of the above-mentioned flip-flop designs has the capability to apply such a vector.
Thus, what is needed is a flip-flop design that not only has low operational power consumption and low leakage power consumption, but that is additionally capable of setting its output to a predefined state that is independent of the data state at either or both of the clock input and the data input to reduce the leakage power consumption of circuitry connected to the output of the flip-flop. What is also needed is a flip-flop whose power consumption is low when its output is held in the predefined state. Finally, some types of circuitry may have low leakage power consumption when the output of the flip-flop is in one state, while other types of circuitry may have low leakage power consumption when the output of the flip-flop is in the other state. Thus, what is also needed is a flip-flop capable of being fabricated in embodiments having low leakage power consumption when the predetermined state corresponds to either output state.
SUMMARY OF THE INVENTION
The invention provides a flip-flop having a sleep mode in which power consumption is reduced. The flip-flop comprises a clock input, a data input, an input stage, an input gate, an output stage and an output clamp. The input gate is interposed between the data input and the input stage and operates in the sleep mode to isolate the input stage from the data input. The output stage is coupled to the input stage and includes an output having a first output state and a second output state. The output clamp operates in the sleep mode to set the output stage to a predetermined state regardless of the data states at the data input and the clock input. The predetermined state is the one of the output states in which the leakage power consumption of the flip-flop is less than in the other of the output states.
The predetermined state may alternatively be the one of the output states in which the leakage power consumption of circuitry connected to the output of the flip-flop is less than in the other of the output states.
As a further alternative, the predetermined state may be the one of the output states in which the leakage power consumption of a digital electronic circuit of which the flip-flop forms part is less than in the other of the output states.
The invention additionally provides a digital electronic circuit having a sleep mode in which power consumption is reduced. The electronic circuit comprises a data input and a flip-flop. The flip-flop includes a clock input, an input stage, an input gate, an output stage and an output clamp. The input gate is interposed between the data input and the input stage, and operates in the sleep mode to isolate the input stage from the data input. The output stage is coupled to the input stage and comprises an output having a first output state and a second output state. The output clamp operates in the sleep mode to set the output to a predetermined state regardless of the data states at the data input and the clock input. The predetermined state is the one of the output states in which the leakage power consumption of the digital electronic circuit is less than i

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