Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1999-08-27
2001-08-07
Wilczewski, Mary (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S758000, C257S760000, C257S637000, C257S640000
Reexamination Certificate
active
06271593
ABSTRACT:
TECHNICAL FIELD
The present invention relates to fabricating conductive components in the manufacturing of microelectronic devices. More specifically, the invention relates to fabricating gold damascene lines and gold interlayer contact vias in integrated circuits.
BACKGROUND OF THE INVENTION
Microelectronic devices are used in computers, communications equipment, televisions and many other products. Typical microelectronic devices include processors, memory devices, field emission displays and other devices that have circuits with small, complex components. In current manufacturing processes, the components of such circuits are generally formed on a substrate or a wafer with conductive, insulative, and semiconductive materials. Each substrate typically has 50-200 microelectronic devices, and each microelectronic device may have several million components. Accordingly, there is a significant drive in the microelectronic device industry to reduce the size and increase the density of components in integrated circuits.
As the density of components in integrated circuits increases, the highly conductive components of an integrated circuit need to be extremely small to provide enough space for the other components. Typical high conductivity components in integrated circuits include runners, damascene lines, contact plugs/vias, dual-damascene lines and other highly conductive components. To provide additional space for the other components of an integrated circuit, the major cross-sectional dimension of many highly conductive components is approximately 0.3 &mgr;m or less. In several applications, the major dimension of highly conductive components is preferably 0.18 &mgr;m or less.
Highly conductive components are formed on top of dielectric layers or in voids in dielectric layers. Conductive lines on top of a dielectric layer, for example, may be formed by depositing a conductive layer over the dielectric layer and then etching the conductive layer to electrically isolate conductors on top of the dielectric layer. Conductive components may also be formed in dielectric layers. For example, damascene lines are a type of conductive line fabricated by etching trenches in a silicon oxide layer down to a silicon nitride etch-stop layer, filling the trenches with a highly conductive material, and then planarizing the wafer down to the silicon oxide layer. Contact vias/plugs are another type of conductive component fabricated by etching vertical holes through a dielectric layer and filling the holes with a highly conductive material. Highly conductive components are generally composed of aluminum, copper or tungsten.
Although conventional conductive components perform adequately for many applications, highly conductive components are beginning to limit the performance of extremely high density integrated circuits with very small components because the resistance per unit length of long, narrow conductive lines is undesirably high. Aluminum is desirable for short or wide conductive features, but it is too resistive for use in long, narrow conductive components. Copper is more conductive than aluminum, but the resistance per unit length of copper conductive components may be too high for long, narrow conductive lines because copper loses an electron to surrounding silicon and silicon oxide layers. To prevent copper molecules in damascene lines from losing an electron to the surrounding silicon oxide layer, the trenches are lined with a barrier layer. However, the barrier layer reduces the cross-sectional area of copper damascene lines thereby exacerbating the problem of high resistance per unit length. Tungsten is also used for conductive components, but it is difficult to fill small voids in dielectric layers with tungsten. Accordingly, aluminum, copper and tungsten conductive lines are not well suited for high density integrated circuits with long, narrow conductive lines having a width of 0.3 &mgr;m or less.
SUMMARY OF THE INVENTION
The present invention is a method for fabricating highly conductive components on microelectronic devices and a substrate structure produced by the method. In one embodiment in accordance with the principles of the present invention, a first dielectric layer is formed over a base layer of a substrate, a second dielectric layer is deposited onto the first dielectric layer, and a third dielectric layer is deposited onto the second dielectric layer. The first, second and third dielectric layers define a first dielectric stratum in which the first and second dielectric layers may be selectively etchable from one another so that the second dielectric layer etches at a faster rate than the first layer in the presence of a selective etchant. After the dielectric layers are deposited onto the substrate, a void is etched through the second and third dielectric layers. The void may be etched in a two part process in which a non-selective etchant etches through the third dielectric layer to an intermediate level in the second dielectric layer, and then a selective etchant etches through the remaining portion of the second dielectric layer to the first dielectric layer. The third dielectric layer is subsequently covered with a conductive layer to fill at least a portion of the void with the conductive material of the conductive layer. The substrate is then planarized to the third layer to leave a portion of the conductive material in the void. The third dielectric layer may have a lower polishing rate than the conductive layer so that the third dielectric layer is a polish-stop layer for the planarizing process.
Although the invention is preferably applicable to forming virtually any type of conductive component on a substrate, it is particularly useful for forming gold components in contact holes and/or trenches. In one embodiment, the first dielectric layer is a first silicon nitride layer, the second dielectric layer is a silicon oxide layer, and the third dielectric layer is a second silicon nitride layer. The first silicon nitride layer is an etch-stop layer with respect to the silicon oxide layer in the presence of a selective etchant, while the second silicon nitride layer is preferably a polish-stop for planarizing the conductive layer down to the second silicon nitride layer. Additionally, the silicon oxide layer is a highly insulative, low capacitance layer to electrically isolate the conductive lines from one another. The first dielectric stratum is particularly useful for fabricating gold conductive components because the first and second silicon nitride layers provide diffusion barriers to inhibit the diffusion into or out of gold conductive lines. Additionally, the first dielectric stratum also provides a structure to form gold conductive lines and contact vias without etching the gold because the void is etched prior to depositing the conductive layer and the second silicon nitride layer is a polish-stop layer that inhibits polishing at a level where gold damascene lines are electrically isolated form one another without additional etching.
In still another embodiment, a second dielectric stratum is constructed on the substrate from the third dielectric layer, a fourth dielectric layer deposited onto the third dielectric layer, and a fifth dielectric layer deposited onto the fourth dielectric layer. The fourth dielectric layer may be a second silicon oxide layer and the fifth dielectric layer may be a third silicon nitride layer. Accordingly, a second void may be etched in the fourth and fifth dielectric layers down to the third dielectric layer to form a space in which a second gold component may be fabricated on the substrate. One advantage of an embodiment of the invention, therefore, is that several dielectric stratums may be stacked on each other to efficiently construct several layers of gold conductive components on a single substrate.
REFERENCES:
patent: 5300813 (1994-04-01), Joshi et al.
patent: 5371047 (1994-12-01), Greco et al.
patent: 5403776 (1995-04-01), Tsuji et al.
patent: 5466639 (1995-11-01), Ireland
patent: 5484740 (1996-01-01), Cho
p
Givens John H.
Lane Richard H.
Micro)n Technology, Inc.
Perkins Coie LLP
Wilczewski Mary
www.perkinscoie.com
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