Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1995-06-06
2001-04-24
Luu, Matthew (Department: 2415)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S089000, C345S182000
Reexamination Certificate
active
06222510
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a display unit in which light emitting pixels are arrayed in a matrix form, and an image signal having a half tone can be displayed.
2. Description of the Prior Art
FIG. 1
is a block diagram showing a conventional display unit disclosed in Japanese Patent Publication (Kokoku) No. 2-709. In
FIG. 1
, reference numeral
1
denotes a matrix display panel such as a fluorescent character display tube,
2
is a driver to drive row electrodes of the matrix display panel
1
, and
3
is another driver to drive column electrodes of the matrix display panel
1
. Display elements (light emitting elements) are disposed at intersections of the row electrodes and the column electrodes, and are turned ON by driving the corresponding row electrode and the corresponding column electrode. Reference numeral
4
denotes a shift register to place an ON/OFF signal from a changing portion
15
on the corresponding column electrode,
5
is a row electrode control circuit to create a drive signal for the row electrode, and
6
is a column electrode control circuit to create a drive signal for the column electrode. The column electrode control circuit
6
latches output of the shift register
4
for a predetermined time interval depending upon a latch signal from a timing generating circuit
8
.
Reference numeral
9
denotes a display control unit to write display data onto a memory
7
,
10
is a selector to feed the memory
7
with any one of a read address and a write address,
11
is a read/write control circuit to feed the selector
10
with a switching signal,
12
is a clock generating circuit to feed a clock signal to the timing generating circuit
8
and the read/write control circuit
11
,
13
is a read address counter to generate the read address, and
15
is the changing portion to transform data read from the memory
7
into the ON/OFF signal for pixel.
The matrix display panel
1
is provided with a structure as shown in FIG.
2
. That is, the display elements are disposed at intersections of a group of signal lines for feeding signals to the column electrodes X
1
to X
m
and a group of signal lines for feeding signals to the row electrodes Y
1
to Y
m
. Thus, the display elements are controlled according to a combination of the signals fed to the two groups of signal lines.
A description will now be given of the operation. The display control unit
9
outputs the display data, an address corresponding to a position at which the display data is displayed, and a timing signal in synchronization with the display data. The timing signal is inputted into the read/write control circuit
11
. The read/write control circuit
11
receives the timing signal as input, and thereafter outputs a signal by which the selector
10
is switched over to the write address. Therefore, the address from the display control unit
9
is fed to the memory
7
as the write address. As a result, the display data can be stored in the memory
7
at an area specified by the write address.
Further, the display data stored in the memory
7
is read out according to the read address which is produced in the read address counter
13
. The read address counter
13
generates an X address (a column address) fed to the column electrode control circuit
6
, a Y address (a row address) fed to the row electrode control circuit
5
, and a comparison signal B. The X address and the Y address are fed into the memory
7
through the selector
10
. In this case, the selector
10
selects the read address according to control by the read/write control circuit
11
. Consequently, it is possible to output data from the memory
7
according to the read address including the X address and the Y address.
Further, the Y address is sent to the row electrode control circuit
5
. The row electrode control circuit
5
decodes the Y address so as to drive the row electrodes Y
1
to Y
m
of the matrix display panel
1
through the driver
2
. The data read from the memory
7
is sent to the changing portion
15
. The changing portion
15
compares the data with the comparison signal B produced in the read address counter
13
so as to generate an ON/OFF signal according to the result of comparison. When the data is greater than the signal B, the ON signal is generated. When the data is equal to or less than the signal B, the OFF signal is generated. Here, ‘1’ shows the ON signal and ‘0’ shows the OFF signal. The ON/OFF signal is disposed in the shift register
4
according to a shift clock from the timing generating circuit
8
. Further, the signal is latched by the column electrode control circuit
6
in response to a latch signal from the timing generating circuit
8
. In response to the latched signal, the column electrode control circuit
6
drives the column electrodes X
1
to X
m
through the driver
3
.
In such a display unit, an image is displayed by sequentially and periodically driving the row electrodes Y
1
to Y
m
, and by switching operation of a signal which is fed to the column electrodes X
1
to X
m
in synchronization with the driving of the row electrodes Y
1
to Y
m
. The display elements can exclusively provide binary representation, that is, any one of ON and OFF. However, when an image signal having a half tone should be displayed, the data in the memory is read out a predetermined number of times, and a cumulative elapsed ON time in each display element is controlled, thereby realizing gray image display.
A more detailed description will now be given of a display operation by way of, as an example, the matrix display panel
1
including a device having a 4-by-4 pixel array. Pixel positions in the matrix display panel
1
correspond to memory addresses in a one-to-one manner, resulting in a relationship as shown in
FIGS. 3 and 4
.
FIG. 3
shows the pixel positions, and
FIG. 4
shows the memory addresses corresponding to the respective pixel positions.
FIG. 5
shows illustrative display data stored in the memory
7
at the respective addresses. As shown in
FIG. 6
, the addresses of the memory
7
can be classified into the X address and the Y address.
FIG. 9
is a timing diagram showing row electrode driving timing and column electrode driving timing.
FIG. 10
is an explanatory view showing the result of the driving.
When the display data corresponding to each pixel includes a 4-bit structure, it is possible to display a 16-scale gray image (because of 2
4
=16). In this case, as shown in
FIG. 7
, the read address counter
13
includes a 2-bit counter
13
a
for generating the X address, a 4-bit counter
13
b
for generating the comparison signal B, and a 2-bit counter
13
c
for generating the Y address. The 2-bit counter
13
b
counts the clock signal from the read/write control circuit
11
to sequentially output values of 0 to 3 corresponding to the column electrodes X
1
to X
4
. The 4-bit counter
13
b
counts a carry signal of the 2-bit counter
13
a
. In the 4-bit counter
13
b
, an initial value is set to zero. The 2-bit counter
13
c
counts a carry signal of the 4-bit counter
13
b
. The initial value of zero in the 2-bit counter
13
c
corresponds to the row electrode Y
1
.
Accordingly, with the comparison signal B of zero and the Y address of zero, four data stored in the first row shown in
FIG. 5
are sequentially read out. As shown in
FIG. 8
, the changing portion
15
comprises, for example, a comparator
15
a
. The comparator
15
a
compares display data A with the comparison signal B so as to output an ON signal when A is greater than B, or output an OFF signal when A is equal to or less than B. As shown in
FIGS. 5 and 6
, the first row sequentially contains data of “15 (in decimal notation),” “10 (in decimal notation),” “12 (in decimal notation),” and “0”. Since the comparison signal B is zero, the changing portion
15
sequentially outputs “1,” “1,” “1,” and “0”. Signals from the changing portion
15
are sequentially inputted into the shift register
4
.
When the respective signals in the first row
Burns Doane , Swecker, Mathis LLP
Luu Matthew
Mitsubishi Denki & Kabushiki Kaisha
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