Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-09-01
2001-03-27
Powell, William (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S692000, C438S719000, C438S723000, C438S724000
Reexamination Certificate
active
06207581
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a contact hole, and particularly to a method of fabricating a node contact hole.
2. Description of the Prior Art
Recently, ultra large scale integration (ULSI) semiconductor technologies have dramatically increased the integrated circuit density on the chips formed on the semiconductor substrate. This increase in circuit density has resulted from downsizing of the individual devices and the resulting increase in device packing density. The reduction in device size was achieved predominantly by recent advances in high resolution photolithography, directional (anisotropic) plasma etching, and other semiconductor technology innovations. However, future requirements for even greater circuit density is putting additional demand on the semiconductor processing technologies and on device electrical requirements.
The rapidly increasing integrated circuit in the number of cells on the DRAM chip and the corresponding reduction in physical size of the capacitor, it is becoming increasingly difficult to fabricate a node contact hole in the capacitor.
FIGS. 1A and 1B
shows the cross-sectional view of a traditional node contact hole. At first, the polysilicon layer
110
is formed on the interpoly dielectric layer
100
. Afterwards, the trench
120
is formed in polysilicon layer
110
, as shown in FIG.
1
A. Next, a portion of the interpoly dielectric layer
100
is etched to expose the land pad
130
, using the polysilicon layer
110
as a hard mask. Then, the polysilicon layer
110
is removed on the interpoly dielectric layer
100
. Finally, the node contact hole
140
is formed in the interpoly dielectric layer
100
, as shown in FIG.
1
B. Due to this contact hole
140
will not obtain the linewidth of 0.1 &mgr;m. Thus, this present invention is disclosed by applying novel processes, and improving the disadvantage.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for forming a node contact hole that substantially reduces linewidth. In one embodiment, the fabrication process includes the steps as follows. At first, a semiconductor structure comprises a metal-oxide-semiconductor field effect transistor (MOSFET) formed in and on the semiconductor substrate. The metal-oxide-semiconductor field effect transistor (MOSFET) includes a shadow trench isolation (STI), a thin oxide, a polycide word line, a source/drain, an oxide spacer, and a cap oxide layer, forming a metal-oxide-semiconductor field effect transistor (MOSFET). The shadow trench isolation is formed in the semiconductor substrate to surround and electrically isolate each device area. The thin oxide is formed, using thermal oxidation. The polycide word line is composed of polysilicon and tungsten silicon (WSi
2
). The source/drain is formed, comprising the lightly doped source/drain and heavily doped source/drain. However, the oxide spacer and the cap oxide layer are formed, usually by depositing an insulating layer such as silicon nitride (Si
3
N
4
) and silicon oxide (SiO
2
). Afterwards, the first interpoly dielectric (IPD1) layer is formed on a semiconductor structure. The landing pad is formed in the first interpoly dielectric layer. The polycide bit line is formed on the first interpoly dielectric layer. Next, the second interpoly dielectric (IPD2) layer is formed on the polycide bit line, the landing pad, and the first interpoly dielectric layer. The defined photoresist layer is formed on the second interpoly dielectric layer, then using reflow and curing processes to form the heated photoresist layer, the heated photoresist layer defining a node contact pattern. Afterwards, a portion of the second interpoly dielectric layer is firstly etched, using the heated photoresist layer as a mask. Thus, the depth is formed in the second interpoly dielectric layer. Then, the heated photoresist layer is removed. Next, the silicon nitride layer is deposited on the second interpoly dielectric layer. The polysilicon layer is deposited on the silicon nitride layer. Afterwards, the polysilicon layer is etched back to expose the silicon nitride layer. A portion of the second interpoly dielectric layer is secondly etched to expose the land pad, using the polysilicon layer as a hard mask. Next, the polysilicon layer is removed on the silicon nitride layer. The silicon nitride layer is removed on the second interpoly dielectric layer. Finally, the node contact hole is formed in the second interpoly dielectric layer.
REFERENCES:
patent: 6004883 (1999-12-01), Yu et al.
patent: 6080674 (2000-06-01), Wu et al.
Wang Chuan-Fu
Wu King-Lung
Powell William
United Microelectronics Corp.
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