Computer graphics processing and selective visual display system – Plural display systems – Tiling or modular adjacent displays
Reexamination Certificate
1998-09-09
2001-01-30
Shalwala, Bipin (Department: 2673)
Computer graphics processing and selective visual display system
Plural display systems
Tiling or modular adjacent displays
C345S003100, C345S182000, C345S213000
Reexamination Certificate
active
06181300
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to resynchronization circuits for image display systems and more particularly to display data format conversion circuits and methods that facilitate display on a plurality of display devices.
BACKGROUND OF THE INVENTION
Today's computer systems incorporate an increasing amount of video and graphic display features to allow laptop computers and other computers to display video images such as movies, television images and graphic images on multiple displays. For example many computers such as a laptop computer may provide an additional display drive port to allow dual display on an LCD display for the laptop as well as a cathode ray tube (CRT) monitor to allow dual display of information, coming from the laptop computer. A problem arises in trying to dynamically synchronize display data for dual display so that the frame rate on both display devices is the same. The problem becomes compounded by the fact that different display devices can have varying refresh rates and display resolutions from frame to frame. For example, an LCD display may have a different resolution from the CRT resolution so that ratiometric expansion is necessary. This may occur for example where the CRT has a screen size of 600×800 pixels whereas the LCD display has a display of 768×1024 pixels.
Where display drive chips, such as computer graphic chips, have an internal clock used for display timing control for one display device, another display control chip may be used having a different internal clock used for display timing for another display device. Typically, these clock frequencies are out of synchronization so the display on each of these screens may be different over time. The synchronization is even more difficult when one of the display devices frame rate's is unstable from time to time, for example, due to signals generated by genlocking. As known in the art, genlocking is used during the reconstruction of an encoded video signal in a video decoder. A video decoder needs to generate a pixel clock that is used in clocking the pixel data into the other processing circuitry or memory. The generation of this pixel clock can be difficult especially when the video source frame rate stability is poor such as with a VCR, One method of overcoming this problem is to store an entire frame in a buffer so that no resynchronization needs to occur. However such a design can require large amounts of expensive memory to accommodate video display for large screens on display devices.
Systems are known that attempt to synchronize displays by allowing a user to preselect a static synchronization offset that is applied irrespective of actual synchronization error. Such systems may use a change in vertical blanking period as a method for facilitating the static resynchronization. However, display systems may have unstable source clocks that vary over time or may otherwise display images at differing display rates from one frame to another due to circuit temperature variations or other variations. Static synchronization systems cannot typically compensate for such deviation thereby resulting in asynchronized multiple displays.
Consequently, there exists a need for a display data format conversion circuit and method that facilitates display on a plurality of display devices when the display devices have different resolutions or when the frame rate of the source is unstable. It would be desirable if such a system minimized the amount of data needed to be stored to decrease the cost of the synchronization system.
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Chih David
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ATI Technologies
Kovalick Vincent E.
Markison & Reckamp, P.C.
Shalwala Bipin
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